// ex1, output c

module ex1;

input  a = {false};
input  b = {false};
output c = {false};
output d = {false};

process ex1;
*[[ skip -> a+; b+; d+; c+; d-; a-
  | skip -> b+; c+
 ]; b-; c- ]
endprocess


// The whole circuit
gate cout;
d | (b & ~a) -> c+
~b -> c-
endgate


// From prs file
// [+c: (d)]
// [+c: (b & ~a)]
// [-c (~b)]

endmodule