9/10/2002

 

  1. Adding code to output .acc files.

Thought:

The hazard checking should write a file for each node of each output in the decomposition. In addition, one file should be written for each output that exposes all nodes.

Questions / Uncertainties:

1.     How do I ensure unique node names?  I currently give each node a number preceded by two x’s (i.e. xx4).  This does not guarantee that the node names will be unique from input names.

2.     Once I have written a .acc file, how do I get a .g file so I can verify?

Solution:            Suppose I start with foobar.csp   My decomp software creates a slew of files, one for each node say:

foobar_a.acc   foobar_b.acc   foobar_c.acc

Then use atacs to create a foobar.g file and, one by one, rename my new .acc files to foobar.acc and verify.

Status:

Software outputs a .acc file for every output in the decomposition.  Rigorously tested using .hse files (ex1-c) and .csp files (x, xor, vme, stack).

Need to finish and test coding to output file for every internal node.

 

  1. Get up to speed on incorporating timing into hazard checking code.

Status:

Meeting with Eric on Friday, Sept 6.  Will write up, and post to web page,  first pass pseudo code for timing algorithm by the end of the week.

 

  1. Revise PowerPoint presentation for SRC.  Due 9/12/2002.

Status:

Need to add figures, redo some slides.  Update will be done by Tuesday am (9/10).

 

  1. Post vitae to SRC web page.  Due now.

Status:

Need to upgrade and post current vitae.

 

  1. Make first pass of poster presentation for SRC.  Due 9/20/2002.

Status:

Not started yet.

 

6.     Type up coloring algorithm.

Status:

Written out by hand.

 

  1. Initial state of state graph. How to handle during coloring?

Current implementation:

Find start state.

Color state 0 or 1 based on Boolean evaluation of node under consideration.

Color all edges leaving state with same color as state (0 or 1).

New implementation:

Find start state.

Color state with a soft 0 or 1 on Boolean evaluation of node under consideration.

Color all edges leaving state with same soft color as state.

Propagate hard colors first (from other edges).

Propagate the soft colors as far as they will go.  Let the soft colors be overridden. When all is done, convert remaining soft colors to hard colors.

Status:

Needs to be coded and tested.

 

  1. Add code to free up memory.

Status:

Need to do.

 

  1. Inverters encountered during hazard checking (Speed Independent).  Do they carry the same hazard properties as preceding nodes?

Current Thought:

Yes except for output/input causality. Are there timing restrictions on when the outputs can fire if they are fed back as inputs? If so, perhaps inverters cannot be ignored.

Chris’s thought:  Always can be ignored for SI.

Current implementation:

Output nodes of inverters are skipped if the inverter is preceded by another inverter or a 2-input Nand gate.

Status:

Done. Will be revisited when coding for timing is added.

 

  1. Acquire and install Vmware for my laptop.

Status:

Vmware downloaded. Need to configure and install Linux 7.3  Can SRC money pay for this?