Agenda

8/30/2002

1. Initial state of state graph. How to handle during coloring?

Current implementation:

Find start state.

Color state 0 or 1 based on Boolean evaluation of node under consideration.

Color all edges leaving state with same color as state (0 or 1).

2. Inverters encountered during hazard checking (Speed Independent). Do they carry the same hazard properties as preceding nodes?

Current Thought:

Yes except for output/input causality. Are there timing restrictions on when the outputs can fire if they are fed back as inputs? If so, perhaps inverters cannot be ignored.

Current implementation:

Output nodes of inverters are skipped if the inverter is preceded by another inverter or a 2-input Nand gate.

3. Kronos test files. What can they be used for and how do I use them?

4. Modifying hse files for outputs with C-elements. See file ex1-c.hse. Why can’t I get this to work.

Summary from previous meeting

8/24/2002

No meeting

To Do List (In order of importance):

8/30/2002

1. Get up to speed on timing (with help from Eric). Getting a slow start here.
2. Run more examples through my software and check for bugs. Modify .hse files to check first and compare results to my SI hazard checking.
3. Continue web page development.
4. Continue work on PowerPoint presentation for SRC conference. Electronic copy due 9/13/2002.
5. Start work on poster presentation for SRC. Due at time of flight (9/20/2002).
6. Post resume to SRC web page.
7. Acquire and install Vmware on my laptop.