Coding issues

Time-line

• October 5 - 25: Implement C-elements from SIS libraries (includes input renaming, level calculation, and testing). Try atomic gates (-ot).
• October 26 - November 15: Implement gC's from SIS libraries (includes input renaming, level calculation, short circuit check). Include common input sub-network equivalence (multiple care terms).
• November 16 - December 13: Finish input permutation code.
• December 14 - 20: Final tune-up, testing, compile results.

Front Burner (October 6 - November 15)

1. Implement C-elements from SIS libraries (includes input renaming and level calculation).
2. Implement gC's from SIS libraries (includes input renaming, level calculation).
3. Add logic check to ensure gC gates do not have a shorted stack.
4. Implement SIS library cells with multiple care terms.

Middle Burner (November 16 - December 20)

1. Append cells with multiple inverters on inputs to library.
2. Matching both legs of nand gates.
3. Code to put an x in the coloring after a hazard is detected.
4. Finish input permutation code.

Back Burner (Whenever)

1. Code to remove zero cost buffers from the covered netlist.
2. Code to do timed hazard checking with level-based events.
3. Code to determine if a reported hazard is true or false.
4. Code to insert buffer delays where mono hazards exist.
5. Modify cge.acc code so the cge is computed from my decomposition.
6. Code to unwind zones using POSETS in timed hazard checking.

Thesis issues

Time-line

• Week of: October 5-11: Chapter 4, Decomposition
• Week of: October 12-18: Chapter 5, Matching / Covering
• Week of: October 19-25: Chapters 4 and 5, Rehash
• Week of: October 26-Nov 1: Chapter 1, Introduction
• Week of: November 2-8: Chapter 2, Background and Semantics
• Week of: November 9-15: Chapter 3, Verification
• Week of: November 16-22: Chapter 4, Decomposition
• Week of: November 23-29: Chapter 5, Matching / Covering
• Week of: November 30-Dec6: Chapter 6, Results
• Week of: December 7-13: Chapter 7, Conclusions / Future Work
• Week of: December 14-20: Final tune-up / Schedule defense

General

1. Redo, expand abstract.
2. Finish acknowledgment, dedication sections.

Introduction

1. Expand on reference citations: GALS, clock skew, automated systems for synchronous design
2. Ready for word-smithing.

Semantics

1. Finish text on gC circuits and an example to illustrate how covering can cause short circuits in a gC mapping.
2. Complete section on hazard definitions.
3. Finish the hazard example explaining how hazards occur.
4. Add covering example of mono. and acknowledgment hazards.
5. Find a good second example. Maybe the half or ebergen circuits (.acc files, not decomp files).

Verification

1. Enhance the discussion of how the SG is derived from the TPN.
2. Weave in more detail in general in this chapter.
3. Add a second example with lots of complexity so I can explain all the nuances of the timing algorithms.
4. Examples of false hazards.

Decomposition

1. Under construction.

Matching/Covering

1. Top-level structure of chapter.

Results

1. What results do I really want to portray?

Conclusions

1. Weave in proper prose to this section.
2. Complete future work section.

References

1. Get hard copies of references.

ICCAD issues

1. Buy airline ticket. Done.
2. Register for conference. Done.
3. Prepare presentation.

Other issues

1. Reimbursement for stay in Utah.