plain CS/EE 5750/6750: Asynchronous Circuit Design

CS/EE 5750/6750: Asynchronous Circuit Design

Chris J. Myers
Lecture 6: Muller Style Synthesis
Chapter 6

Muller Circuits

Muller Circuit Design

  • Translate higher level specification into a state graph.
  • If not complete state coded, change the protocol or add new internal state signal(s).
  • Derive logic using modified logic minimization procedure.
  • Map design to gates in a given gate library.

Overview

  • Formal definition of speed independence.
  • State graphs.
  • State assignment of Muller circuits.
  • Logic minimization of Muller circuits.
  • Technology mapping of Muller circuits.

Complete Circuits

  • To design a speed independent circuit, must have complete information about both the circuit and its environment.
  • We restrict our attention to complete circuits.
  • A complete circuit C is defined by a finite set of states, S.
  • At any time, C is said to be in one of these states.

Allowed Sequences

  • Behavior of a complete circuit is defined by set of allowed sequences of states.
  • Each allowed sequence can be either finite or infinite, and the set of allowed sequences can also be finite or infinite.
  • The sequence ( s1, s2, s3, ... ) says that state s1 is followed by state s2, but it does not state at what time.

Properties of Allowed Sequences

  • For a sequence ( s1, s2, ... ), consecutive states must be different (i.e., si si+1).
  • Each state s S is the initial state of some allowed sequence.
  • If ( s1, s2, s3, ... ) is allowed sequence then so is ( s2, s3, ... ).
  • If ( s1, s2, ... ) and ( t1, t2, ... ) are allowed sequences and s2 = t1, then ( s1, t1, t2, ... ) is also an allowed sequence.

Simple Example Complete Circuit

  • Consider a complete circuit composed of four states, S = { a, b, c, d }, which has the following two allowed sequences:

    1. a, b, a, b,
    2. a, c, d

  • The sequences above imply the following allowed sequences:

    1. b, a, b, a,
    2. c, d
    3. d
    4. a, b, a, c, d
    5. a, b, a, b, a, c, d
    6. b, a, c, d
    7. etc.

State Diagram For Simple Example

Figure

R-related and R-sequences

  • Two states si, sj S are R-related, (denoted si R sj) when:

    1. si = sj or
    2. si, sj appear consecutively in some allowed sequence.

  • A sequence ( s1, s2, ..., sm ) is an R-sequence if si R si+1 for each 1 i m-1.

The Followed and Equivalence Relations

  • A state si is followed by a state sj (denoted si F sj) if there exists an R-sequence ( si, ..., sj ).
  • The F-relation is reflexive and transitive, but not necessarily symmetric.
  • If two states si and sj are symmetric under the F-relation (i.e., si F sj and sj F si), they are said to be equivalent (denoted si E sj).

Equivalence Classes

  • The equivalence relation E partitions the finite set of states S of any circuit into equivalence classes of states.
  • The F-relation can be extended to these equivalence classes.
  • If A and B are two equivalence classes, then A F B if there exists states a A and b B such that a F b.
  • If a A and b B and A F B, then a F b.

Speed Independence

  • For any allowed sequence, there is a definite last class which is called the terminal class.
  • A circuit C is speed independent with respect to a state s if all allowed sequences starting with s have the same terminal class.

Equivalence Classes for Simple Example

Figure

State Graphs

  • Muller circuits are typically modeled using a state graph (SG).
  • State graphs can be derived from any of the graphical models.
  • A SG is modeled by the tuple N, T, S, s0, d, lS, lT :

    • N = I O is the set of signals.
    • T = TI TO is the set of transitions.
    • S is the set of states.
    • s0 S is the initial state.
    • d S × T × S is the set of state transitions.
    • lS : S (N {0,1}) is the state labeling function.
    • lT : T N is the transition labeling function.

State Labeling

  • Each state s is labeled with a binary vector s(0), s(1), , s(n) where s(i) is either 0 or 1 indicating the value returned by lS.
  • If in a state si, there exists a transition on signal ui to state sj (i.e., $(si,t,sj) d . lT(t) = ui), then ui is excited.
  • If there is no such transition, the signal ui is in equilibrium.
  • The value that each signal is tending to is called its implied value.
  • If the signal is excited, then the implied value of ui is [`s(i)].
  • If the signal is in equilibrium, then the implied value of ui is s(i).
  • The implied state s(0), s(1), ..., s(n) are the implied values.
  • The function G: S 2N returns the set of excited signals in a given state (i.e., G(s) = { ui | s(i) s(i) }).

A Simple Speed Independent Circuit

Figure Figure

Consistent State Assignment

  • A well-formed SG must have a consistent state assignment.
  • A SG has a consistent state assignment if each state transition (si,t,sj) d can be labeled such that the only signal to change value is the one which experienced a transition (i.e., lT(t)).
  • In other words, a SG has a consistent state assignment if
    "(si,t,sj) d. "u N
    .
    (lT(t) u lS(si)(u) = lS(sj)(u))
    (lT(t) = u lS(si)(u) lS(sj)(u))

Allowed Sequences on State Graphs

  • An allowed sequence of states ( s1, s2, ... ) is any sequence of states satisfying the following three conditions:

    1. No two consecutive states si and si+1 are equal.
    2. For any state sj+1 and signal ui one of the following is true:
      sj+1(i)
      =
      sj(i)
      sj+1(i)
      =
      sj(i)
    3. If there exists a signal ui and a state sj such that sj(i) = sr(i) and sj(i) = sr(i) for all sr in the sequence following sj, then
      sj(i) = sj(i)

Totally Sequential

  • A circuit is totally sequential with respect to a state s if there is only one allowed sequence starting with s.

Figure
Figure
Semi-Modularity

  • A circuit is semi-modular if in each state in which multiple signals are excited, that in the states reached after one signal has transitioned, that the remaining signals are still excited.
    "si S . "t1, t2 T .  (si, t1, sj) d(si, t2, sk) d
    $sl S . (sj, t2, sl) d(sk, t1, sl) d
  • A totally sequential circuit is semi-modular but the converse is not necessarily true.
  • A semi-modular circuit is also speed independent, but again the converse is not necessarily true.

Output Semi-Modularity

  • Input transitions are typically allowed to be disabled by other input transitions, so another useful class of circuits are those which are output semi-modular.
  • A SG is output semi-modular if only input signal transition can disable other input signal transitions.
    "si S . "t1 T0 . "t2 T .  (si, t1, sj) d(si, t2, sk) d
    $sl S . (sj, t2, sl) d(sk, t1, sl) d

A Simple Speed Independent Circuit

Figure Figure

A Simple Semi-Modular Speed Independent Circuit

Figure Figure

Excited States

  • It is often useful to be able to determine in which states a signal is excited to rise or fall.
  • The sets rising(u) and falling(u) are defined as follows:
    rising(u)
    =
    { s | lS(s)(u) = 0 $(s,t,s) d. lT(t) = u }
    falling(u)
    =
    { s | lS(s)(u) = 1 $(s,t,s) d. lT(t) = u }

Quiescent States

  • For each signal u, there are two sets of stable, or quiescent states.
  • The sets high(u) and low(u) are defined as follows:
    high(u)
    =
    { s | lS(s)(u) = 1 s \not falling(u) }
    low(u)
    =
    { s | lS(s)(u) = 0 s \not rising(u) }

Excitation Regions

  • An excitation region for signal u is a maximally connected subset of either rising(u) or falling(u).
  • If it is a subset of rising(u), it is a set region (denoted ER(u ,k)).
  • Similarly, a reset region is denoted ER(u ,k).

Switching Regions

  • The switching region for a transition u*, SR(u*,k), is the set of states directly reachable through transition u*:
    SR(u*,k)
    =
    { sj | $si ER(u*,k).(si,u*,sj) d}

Distributive State Graphs

  • A state graph is distributive if each excitation region has a unique minimal state.
  • A minimal state for ER(u*,k) is a state in ER(u*,k) which cannot be directly reached by any other state in ER(u*,k).
  • More formally, a SG is distributive if:
    "ER(u*,k) . $exactly one sj ER(u*,k) . 
    $si ER(u*,k) . (si,t,sj) d

Trigger Signals

  • Each cube in the implementation is composed of trigger signals and context signals.
  • For an excitation region, a trigger signal is a signal whose firing can cause the circuit to enter the excitation region.
  • The set of trigger signals for an excitation region ER(u*,k) is:
    TS(u*,k)
    =
    { u | $si,sj S . (lT(t) = u) ((si, t, sj) d)
    (si \not ER(u*,k)) (sj ER(u*,k)) }
  • Any non-trigger signal which is stable in the excitation region can potentially be a context signal.

Context Signals

  • Any non-trigger signal which is stable in the excitation region can potentially be a context signal.
  • The set of context signals for an excitation region ER(u*,k) is:
    CS(u*,k)
    =
    { ui | "sj, sk ER(u*,k) . sj(i) = sk(i) }

The Passive/Active Wine Shop: Petri-net

Figure

The Passive/Active Wine Shop: State Graph
Figure

The Passive/Active Wine Shop: State Sets

rising(req_patron)
=
{ R00R , 100R }
falling(req_patron)
=
{ R10F , 110F }
high(req_patron)
=
{ RR01 , 1R01 }
low(req_patron)
=
{ RF00 , 1F00 , R000 ,
10R0 , F010 , 00F0 }
ER(req_patron+,1)
=
{ R00R , 100R }
ER(req_patron-,1)
=
{ R10F , 110F }
SR(req_patron+,1)
=
{ RR01 , 1R01 }
SR(req_patron-,1)
=
{ RF00 , 1F00 }

The Passive/Active Wine Shop: Signal Sets

TS(req_patron+,1)
=
{ ack_wine }
TS(req_patron-,1)
=
{ ack_patron }
CS(req_patron+,1)
=
{ ack_patron }
CS(req_patron-,1)
=
{ ack_wine }

Unique State Codes (USC)

  • Two states have unique state codes (USC) if they are labeled with different binary vectors.
    USC(si,sj)
    lS(si) lS(sj)
  • A SG has USC if all states pairs have USC.
    USC(S)
    "(si, sj) S ×S .  USC(si,sj)

Complete State Codes (CSC)

  • Two states have complete state codes (CSC) if they either have USC or if they do not have USC but do have the same output signals excited in each state.
    CSC(si,sj)
    USC(si,sj  G(si) To = G(sj) To
    CSC(S)
    "(si,sj) S ×S  .  CSC(si,sj)
  • A set of state pairs which violate the CSC property is defined as:
    CSCV(S) = { (si,sj) S × S |  CSC(si,sj) }

The Passive/Active Wine Shop: State Graph
Figure

The CSC Problem

  • If a circuit does not have USC but has CSC, then the present state/next state relationship is not unique for input signals.
  • Circuit only synthesized for outputs, so not a problem.
  • When a circuit does not have CSC, the present state/next state relationship for output signals is ambiguous.
  • Could reshuffle the protocol as described earlier.
  • Now introduce method for inserting state variables.

Insertion Points

  • Need to insert a rising and falling transition for new signal.
  • A transition point is TP = (ts, te), where ts is a set of start transitions and te is a set of end transitions.
  • The transition point represents the location in the protocol in which a transition on a new state signal is to be inserted.
  • In a graphical model, such as a PN, a TP represents a transition with incoming arcs from ts and with outgoing arcs to te.
  • An insertion point is IP = (TPR, TPF), where TPR is for the rising transition and TPF is for the falling transition.

Transitioning States

  • It is necessary to determine in which states a transition can occur when inserted into a TP.
  • The transtion on the new state signal becomes excited when the circuit enters t ts SR(t).
  • Once this transition becomes excited it may remain excited in any subsequent states until there is a transition in te.
  • The set of states in which a new transition is excited is defined recursively as follows:
    S(TP)
    =
    { sj | sj t tsSR(t)
    ($(si,t,sj) d . si S(TP) t \not te) }

TP = ({ req_patron+ }, { req_patron- })
Figure

Insertion Point Explosion

  • The set of all possible insertion points includes all combinations of transitions in ts and te for TPR and TPF.
  • Upper bound on the number of possible insertion points is |2T|4.
  • Fortunately, many of these insertion points can be quickly eliminated because they either:

    • Never lead to a satisfactory solution of the CSC problem or
    • The same solution is found using a different insertion point.

Transition Point Restrictions

  • A transition point must satisfy the following four restrictions:

    1. ts te =
    2. "t te .  t \not TI
    3. "t1, t2 ts .   t1 ||t2
    4. "t1, t2 te .   t1 ||t2

Transition Point Examples

( { ack_wine+ }
,
{ ack_wine- } )
( { ack_wine- }
,
{ req_patron- })
( { ack_wine- }
,
{ ack_wine+ } )
( { ack_wine-, req_patron+ }
,
{ req_patron- })
( { req_wine+, req_patron- }
,
{ ack_wine+ } )
( { req_wine+, req_patron- }
,
{ ack_wine- } )
( { req_wine+, ack_patron- }
,
{ ack_wine+ } )
( { req_wine+, ack_patron- }
,
{ ack_wine- } )
( { req_wine- }
,
{ ack_wine- } )

Transition Point Examples

( { req_patron+ }
,
{ req_patron+ } )
( { req_patron+ }
,
{ req_patron- } )
({ req_patron+ }
,
{ ack_patron+ } )
({ req_patron+ }
,
{ ack_wine+, req_patron- } )
( { ack_patron+ }
,
{ req_patron- } )

Insertion Point Restrictions

  • Each IP = (TPR, TPF) must be checked for compatibility.
  • Two TP's are incompatible when either of the following is true:
    TPR(ts)     TPF(ts)   =  
    TPR(te)     TPF(te)   =  
  • An incompatible insertion point always creates an inconsistent state assignment.
  • Example:
    IP
    =
    ( { ack_wine+ }, { ack_wine- } ),
    ( { req_wine+, req_patron- }, { ack_wine- } )

State Graph Coloring

  • Need to determine effect of inserting a state variable in an IP.
  • Could be done by inserting the state signal and finding new SG.
  • This approach is unnecessarily time consuming and may produce a SG with an inconsistent state assignment.
  • Instead, the orignal SG is partitioned into four subpartitions cooresponding to the rising, falling, high, and low sets for the new state signal.

State Graph Coloring Procedure

  • States in S(TPR) are colored as rising.
  • States in S(TPF) are colored as falling.
  • If a state to be colored falling is already rising, then this IP leads to an inconsistent state assignment and must be discarded.
  • All states following those colored rising before reaching any colored falling are colored as high.
  • Similarly, all states between those colored as falling and those colored as rising are colored as low.
  • While coloring high or low, if a state to be colored is found to already have a color, then again the IP leads to in inconsistent state assignment.

IP(({ req_patron+ }, { req_patron- }), ({ ack_wine- }, { ack_wine+ } ))
Figure

IP(({ req_patron+ }, { req_patron- }), ({ ack_wine+ }, { ack_wine- } ))
Figure

Insertion Point Primary Cost Function

  • The primary component of the cost function is the number of remaining CSC violations after a state signal is inserted.
  • Eliminate from CSCV any pair of violations in which one state is colored high while the other is colored low.
  • States that had a USC violation may now have a CSC violation.
  • For each pair of states with a USC violation (but not a CSC violation), if one is colored rising while the other is colored low, there is now a CSC violation.
  • Similarly, if one is colored falling and the other is colored high, there is also a new CSC violation.
  • Each new CSC violation must be added to the total remaining.

Insertion Point Secondary Cost Functions

  • First, solutions which solve CSC violations even at the cost of adding new CSC violations are prefered.
  • An IP which solves 1 CSC violation and converts 1 USC violation into a CSC violation is prefered over one which does not remove any CSC violations.
  • The IP with the smallest sum |TPR(te)| + |TPF(te)|.
  • The IP with the smallest sum |TPR(ts)| + |TPF(ts)|.

State Signal Insertion: Petri-net

  • State signal can be inserted into a Petri-net by adding arcs from each transition in ts to the new state signal transition.
  • Similarly, arcs are added from the new transition to each of the transitions te.
  • The same steps are followed for the reverse transition.
  • The state signal is assigned an initial value based on the coloring of the initial state.
  • At this point, a new SG can be found.

The Passive/Active Wine Shop with CSC: Petri-net

Figure

The Passive/Active Wine Shop with CSC: State Graph
Figure

State Signal Insertion: State Graph

  • Alternatively, the new SG could be found directly.
  • Each state in the original SG is extended to include new signal.
  • If a state is colored low, then the new signal is '0'.
  • If a state is colored high, then the new signal is '1'.
  • If a state is colored rising then it must be split into two new states, one with new signal 'R' and the other has it as '1'.
  • If a state is colored falling then it must be split into two new states, one has the new signal 'F' and the other has it as '0'.

Multiple Signal Insertion

  • Often the insertion of a single state signal is not sufficient to eliminate all CSC violations.
  • After deriving the new SG, must find its CSC violations.
  • If new SG has CSC, then the state assignment terminates.
  • If not, the procedure repeats, this time taking the new SG as the starting point and attempts to add an additional state signal.

Hazard-free Logic Synthesis

  • Requires modified minimization to obtain hazard-free logic.
  • Modifications needed are dependent upon technology.
  • We consider the following technologies:

    1. Complex gates
    2. Generalized C-elements
    3. Basic gates

Atomic Gate Implementation

  • Assume that each output to be synthesized is implemented using a single complex atomic gate.
  • A gate is atomic when its delay is modeled by a single delay element connected to its output.

Figure

Atomic Gate Logic Synthesis

  • On-set for a signal u is the set of states in which u is excited to rise or stable high.
  • Off-set is set of states in which u is excited to fall or stable low.
  • DC-set is the set of all unreachable states, or equivalently those states not included in either the on-set or off-set.
    on-set
    =
    { lS(s) | s (rising(u) high(u)) }
    off-set
    =
    { lS(s) | s (falling(u) low(u)) }
    DC-set
    =
    {0,1}|N| - (on-set off-set)
  • Find primes using recursive procedure described earlier.
  • Setup and solve a covering problem.

Figure
Atomic Gate: Example

on-set
=
{ 10000, 10100, 00100, 10101 }
off-set
=
{ 00101, 00001, 10001, 00011, 10011, 01011, 00010,
 10010, 01010, 11010, 01000, 11000, 11011, 00000 }
DC-set
=
{ 00110, 00111, 01001, 01100, 01101, 01110, 01111,
 10110, 10111, 11001, 11100, 11101, 11110, 11111 }
primes
=
{ 1-1-, -11-, -11-, -1-0, -1-01, 10-00 }
1-1-
-11-
-11-
-1-0
-1-01
10-00
10000
-
-
-
-
-
1
10100
1
-
-
1
-
1
00100
-
-
-
1
-
-
10101
1
-
-
-
-
-

Passive/Active Shop: Atomic Gate Circuit

Figure Figure

Generalized C-element (gC) Implementation

Figure

gC Logic Synthesis

  • Two minimization problems must be solved for each signal u: set of the function (i.e., set(u)) and reset (i.e., reset(u)).
  • For set(u):

    • On-set is states in which u is excited to rise.
    • Off-set is states in which u is excited to fall or is stable low.
    • DC-set is stable high and unreachable states.
    • Stable high states are don't cares, since once a gC is set its feedback holds its state.
      on-set
      =
      { lS(s) | s (rising(u) }
      off-set
      =
      { lS(s) | s (falling(u) low(u)) }
      DC-set
      =
      {0,1}|N| - (on-set off-set)

gC Logic Synthesis

  • For reset(u):

    • On-set is states in which u is excited to fall.
    • Off-set is states in which u is either rising or high.
    • DC-set is stable low and unreachable states.
      on-set
      =
      { lS(s) | s (falling(u) }
      off-set
      =
      { lS(s) | s (rising(u) high(u)) }
      DC-set
      =
      {0,1}|N| - (on-set off-set)

  • Can now apply standard methods to find a minimum number of primes to implement the set and reset functions.

Figure
gC Circuit: Example

on-set
=
{ 10000 }
off-set
=
{ 00101, 00001, 10001, 00011, 10011, 01011, 00010,
 10010, 01010, 11010, 01000, 11000, 11011, 00000 }
DC-set
=
{ 00110, 00111, 01001, 01100, 01101, 01110, 01111,
 10110, 10111, 11001, 11100, 11101, 11110, 11111,
 10100, 00100, 10101 }
primes
=
{ 1-1-, -11-, -11-, -1-0, -1-01, 10-00 }
1-1-
-11-
-11-
-1-0
-1-01
10-00
10000
-
-
-
-
-
1

Passive/Active Shop: gC Circuit

Figure Figure

A Simple Example

Figure Figure

Combinational Optimization

Figure

Combinational Optimization

  • If set(u) is on in all states in which u should be rising or high, then the state holding element can be removed.
  • The implementation for u is simply equal to the logic for set(u).
  • If reset(u) is on in all states in which u should be falling or low, then the signal u can be implemented with [`(reset(u))].

Gate-Level Hazard

Figure Figure

Standard C-implementation

Figure

  • Structure similar to gC-implemenation, but built differently.
  • Each AND gate, called a region function, implements a single (or possibly a set of) excitation region(s) for the signal u.
  • In gC-implemenation, an excitation region can be implemented by multiple product terms.
  • A region function may need to be implemented using SOP.

Region Function Operation

  • Each region function must:

    • Turn on only when it enters a state in its excitation region.
    • Turn off monotonically sometime after the signal u changes.
    • Must stay off until the excitation region is entered again.

  • To guarantee this behavior, each region function must satisfy certain correctness constraints.
  • Requires a modified logic minimization procedure.

Region Function Covers

  • Each region function is implemented using a single atomic gate, corresponding to a cover of an excitation region.
  • A cover C(u*,k) is a set of states for which the corresponding region function evaluates to one.
  • First present a method in which each region function only implements a single excitation region.
  • Later extend the method to allow a single region function to implement multiple excitation regions to promote gate sharing.

Correctness Constraints: Intuition

  • Each region function can only change when it is needed to actively drive the output signal to change.
  • Consider a region function for a set region:

    • Gate turns on when circuit enters a state in the set region.
    • When region function changes to 1, it excites the OR gate.
    • When the OR gate changes to 1 in excites the C-element (assuming the reset network is low) to set u to 1.
    • Only after u rises can the region function be excited to fall.
    • The region function then must fall monotonically.
    • The signal u will not be able to fall until the region function has fallen and the OR gate for the set network has fallen.
    • Once region function falls, it cannot be excited again until the circuit again enters a state in this set region.

Covering Constraint

  • The reachable states in a correct cover must include the entire excitation region.
  • It must not include any states outside the union of the excitation region and associated quiescent states.
    ER(u*,k) [C(u*,k) S] [ER(u*,k) QS(u*)]
    where QS(u+) = high(u) and QS(u-) = low(u).

Entrance Constraint

  • A cover must only be entered through excitation region states.
    [ (si,t,sj) dsi \not C(u*,k)sj C(u*,k) ] sj ER(u*,k)

Excitation Region Implicants

  • The goal of logic minimization is to find an optimal SOP for each region function that satisfies the definition of a correct cover.
  • An implicant of an excitation region is a product that may be part of a correct cover.
  • c is an implicant of an excitation region ER(u*,k) if the reachable states covered by c are a subset of the states in the union of the excitation region and associated quiescent states.
    [c S] [ER(u*,k) QS(u*)].

Gate Level Logic Synthesis: Set Regions

  • For each set region ER(u+,k):

    • On-set is those states in ER(u+,k).
    • Off-set includes states in which u is falling or low, and also the states outside this excitation region where u is rising.
    • This additional restriction is necessary to make sure that a region function can only turn on in its excitation region.
      on-set
      =
      { lS(s) | s (ER(u+,k) }
      off-set
      =
      { lS(s) | s (falling(u) low(u))
                       (rising(u) - ER(u+,k)) }
      DC-set
      =
      {0,1}|N| - (on-set off-set)

Gate Level Logic Synthesis: Reset Regions

  • For a reset region ER(u-,k):
    on-set
    =
    { lS(s) | s (ER(u-,k) }
    off-set
    =
    { lS(s) | s (rising(u) high(u))
                     (falling(u) - ER(u-,k)) }
    DC-set
    =
    {0,1}|N| - (on-set off-set)

Gate Level Circuit: Example

Figure

Gate Level Circuit: Example

  • There are two set regions for c: ER(c+,1) = 0100 and ER(c+,2) = 1101.
  • Let's examine the implementation of ER(c+,1).
    on-set
    =
    { 0100 }
    off-set
    =
    { 0000, 1000, 0010, 1100, 1101 }
    DC-set
    =
    { 0001, 0011, 0101, 0110, 0111,
     1001, 1010, 1011, 1110, 1111 }
  • The primes found are as follows:
    primes
    =
    { 01-, 1-1-, -11-, 0-1, -0-1, -11 }

Implied States

  • The entrance constraint creates a set of implied states for each implicant c (denoted IS(c)).
  • A state s is in IS(c) if it is not covered by c but due to the entrance constraint must be covered if c is to be part of the cover.
  • A state si is in IS(c) for ER(u*,k) if it is not covered by c, and si leads to sj which is both covered by c and not in ER(u*,k).
    IS(c) = { si | si \not c $sj.(si,t,sj) d(sj c)(sj \not ER(u*,k)) }
  • This means that the product c becomes excited in a quiescent state instead of an excitation region state.
  • If there no other product in the cover contains this implied state, the cover violates the entrance constraint.

Existence of a Prime Cover

  • An implicant may have implied states that are outside the excitation region and the cooresponding quiescent states.
  • These implied states may not be covered by any other implicant.
  • If this implicant is the only prime which covers some excitation region state, then no cover can be found using only primes.

Existence of a Prime Cover: Example

Figure

Candidate Implicants

  • An implicant is a candidate implicant if there does not exist an implicant which properly contains it with a subset of the implied states.
  • ci is a candidate implicant if there does not exist an implicant cj that satisfies the following two conditions:
    cj
    ci
    IS(cj)
    IS(ci).
  • Prime implicants are always candidate implicants, but not all candidate implicant are prime.
  • An optimal cover exists using only candidate implicants.
  • NOTE: similar to prime compatibles.

Candidate Implicant Algorithm

xxx ¯ xxx ¯ xxx ¯ xxx ¯ xxx ¯ xxx ¯ xxx ¯ (SGP){ done =
 for(k = |largest(P)|; k 1; k-) {
  foreach(q P;  |q| = k)  enqueue(C,q)
  foreach(c C;  |c| = k) {
   if(IS(SG,c) = ) continue
   foreach(s lit_extend(c)) {
    if(s done) continue
    Gs = IS(SG,s)
    prime = true
    foreach(q C; |q| k) {
     if (s q) {
      Gq = IS(SG,q)
      if (Gs Gq) {
       prime = false;
       break } } }
    if(prime = 1) enqueue(C,s)
    done = done{s} } } } }

Candidate Implicant Algorithm Example

Formulating the Covering Problem

  • Introduce a Boolean variable xi for each candidate implicant ci.
  • The variable x1 = 1 when the candidate implicant is included in the cover and 0 otherwise.
  • Using these variables, we can construct a product of sums representation of the covering and entrance constraints.

Covering Clauses

  • A covering clause is constructed for each state s in ER(u*,k).

  • Each clause consists of disjunction of candidates that cover s.


    i: s ci 
    xi.
  • ER(u*,k) = 0100 which is included in only candidate implicants c1 (01-) and c2 (010-):
    (x1 + x2)

Closure Clauses

  • For each candidate implicant ci, a closure clause is constructed for each of its implied states s IS(ci).
  • Each closure clause represents an implication if a candidate implicant used, its implied states must be covered.

    xi
     
        

    j: s cj 
    xj.
  • The candidate implicant c1 (01-) has implied state 0110.
  • 0110 included in implicants c3 (1-1-) and c5 (-11-).
    (
    x1
     
    + x3 + x5)
  • Complete formula: (x1 + x2)([`(x1)] + x3 + x5)[`(x3)] [`(x5)] [`(x8)]

Setting Up the Constraint Matrix

  • Find xi's that satisfy function with minimum cost.
  • Since there are negated variables, the covering problem is binate.
  • The constraint matrix has one row for each clause and one column for each candidate implicant.
  • Rows divided into a covering section and a closure section.
  • Covering section: row for each excitation region state s, with a 1 in every column with a candidate implicant that includes s.
  • Closure section: row for each implied state s of each candidate implicant ci, with a 0 in the column corresponding to ci and a 1 in each column with a candidate implicant cj that covers s.

Constraint Matrix for ER(c+,1)

01-
010-
1-1-
101-
-11-
0-1
-0-1
-11
1
1
1
-
-
-
-
-
-
2
0
-
1
-
1
-
-
-
3
-
-
0
-
-
-
-
-
4
-
-
-
-
0
-
-
-
5
-
-
-
-
-
-
-
0

A Simple Example

Figure Figure

Combinational Optimization

  • Can remove the C-element when the covers for the set function for a signal u include all states where u is rising or high.


    l 
    C(u+,l) rising(u) high(u)
  • Or the covers for the reset function include all states where u is falling or low.


    l 
    C(u-,l) falling(u) low(u)

Gate Sharing

  • Can allow a single gate to implement multiple excitation regions.
  • Need to modify the covering constraint to allow the cover to include states from other excitation regions.
    ER(u*,k) [C(u*,k) S]


    l 
    ER(u*,l) QS(u*)
  • The entrance constraint must also be modified to allow the cover to be entered from any corresponding excitation region state.
    [ (si,t,sj) dsi \not C(u*,k)sj C(u*,k) ] s

    l 
    ER(u*,l)
  • An additional constraint is also now necessary to guarantee that a cover either includes an entire excitation region or none of it.
    ER(u*,l) \not C(u*,k) ER(u*,l) C(u*,k) =

Gate Sharing Example: SG
Figure

Example: No Sharing

  • ER(c+,1) = 100 and ER(c+,2) = 110.
  • Using the earlier constraints, the primes are found to be:
    primes(c+,1)
    =
    { 10-, 1-1, -11 }
    primes(c+,2)
    =
    { 11-, 1-1, -11 }

Gate Sharing Example: Original Circuit

Figure

Example: Sharing

  • ER(c+,1) = 100 and ER(c+,2) = 110.
  • Using the new constraints, the primes are found to be:
    primes(c+,1)
    =
    { 1-, -11 }
    primes(c+,2)
    =
    { 1-, -11 }

Gate Sharing Example: Optimized Circuit

Figure

The Single Cube Algorithm

  • Previous methods often more general than necessary since many region functions can be built using a single product, or cube.
  • Now present a more efficient algorithm which finds an optimal single-cube cover for each region function, if one exists.

Excitation Cubes

  • In a single-cube cover, all literals must correspond to signals that are stable throughout the excitation region.
  • ER(u*,k) is approximated using an excitation cube.
  • The excitation cube is the supercube of the states in the excitation region and defined on each signal v as follows:
    EC(u*,k)(v)



    0
    if "s ER(u*,k) . s(v) = 0
    1
    if "s ER(u*,k) . s(v) = 1
    -
    otherwise
  • If a signal has a value of 0 or 1 in the excitation cube, the signal can be used in the cube implementing the region.
  • The set of states implicitly represented by the excitation cube is always a superset of the set of excitation region states.

Trigger Cubes

  • The set of trigger signals for ER(u*,k) can also be represented with a cube called a trigger cube.
  • TC(u*,v) is defined as follows for each signal v:
    TC(u*,k)(v)



    sj(v)
    If $(si,t,sj) d .  lT(t) = v 
    (si \not ER(u*,k)) (sj ER(u*,k))
    -
    otherwise
  • The single cube cover of an excitation region must contain all its trigger signals (i.e., C(u*,k) TC(u*,k)).
  • Therefore, all trigger signals must be stable (i.e., EC(u*,k) TC(u*,k)).

Example: Excitation and Trigger Cubes

Figure

Excitation and Trigger Cubes

u*,k EC(u*,k) TC(u*,k)
c+, 1 0100 -1-
c+, 2 1101 -1
c-, 1 0010 -0-
d+, 1 1100 -1-
d-, 1 1111 -1-

Violating States

  • Goal is to find smallest product C(u*,k) where
    EC(u*,k) C(u*,k) TC(u*,k)
    and satisfies the required correctness constraints.
  • Begin with a cube consisting only of the trigger signals.
  • If this cover contains no states that violate the required correctness constraints, we are done.
  • If not, context signals must be added to the cube to remove any violating states.
  • For each violation detected, the procedure determines the choices of context signals which would exclude the violating state.
  • Finding smallest set of context signals is a covering problem.

Violating States: gC Circuits

  • In gC circuits, for a set region a state is a violating state when the trigger cube intersects the falling or low sets.
  • Similarly, for a reset region, a state is a violating state when the trigger cube intersects the rising or high sets.
    V(u+,k)
    =
    { s | s TC(u+,k) s falling(u) low(u) }
    V(u-,k)
    =
    { s | s TC(u-,k) s rising(u) high(u) }

Example: Violating States

Figure

Context Signal Choices

  • Determine context signals which remove these violating states.
  • A signal is allowed to be a context signal if it is stable in the excitation cube (i.e., EC(u*,k)(v) = 0 or EC(u*,k)(v) = 1).
  • A context signal removes a violating state when it has a different value in the excitation cube and the violating state.
  • In other words, a context signal v removes a violating state s when EC(u*,k)(v) = [`s(v)].

Example: Context Signals

Figure

Setting Up the Covering Problem

  • The constraint matrix has a row for each violating state and a column for each context signal.
  • The constraint matrix for ER(d+,1) is shown below:
    a
    c
    d
    1111
    -
    1
    1
    1110
    -
    1
    -
    0110
    1
    1
    -
    0100
    1
    -
    -

SCSI Example: Excitation Cubes

SCSI Example: Quiescent States

SCSI Example: Trigger Cubes

SCSI Example: Initial Circuit

SCSI Example: Covering Violations

SCSI Example: Context Signals

SCSI Example: Constraint Matrix

SCSI Example: Final Circuit

Gate Level Circuits: Cover Violations

  • For gate level circuits, must use covering and entrance constraints.
  • For each ER(u*,k), find all states in the initial cover, TC(u*,k), which violate the covering constraint:
  • A state s in TC(u*,k) is a violating state if:

    • The signal u has the same value but is not excited,
    • Is excited in the opposite direction, or
    • Is excited in the same direction but the state is not in the current excitation region.

Example: Cover Violations

Figure

Gate Level Circuits: Entrance Violations

  • Must check state transitions for potential entrance violations.
  • For each state transition (si,t,sj), this is possible when sj is a quiescent state, sj is in the initial cover, and lT(t) excludes si.

    1. sj high(u) for a set region and sj low(u) for a reset region
    2. sj TC(u*,k)
    3. EC(u*,k)(lT(t)) = [`(s(lT(t)))]

  • For each potential entrance violation, a context signal must be added which excludes sj from the cover when lT(t) is included.
  • If lT(t) is a trigger signal, then the state sj is a violating state.
  • If lT(t) is a possible context signal choice, then sj becomes a violating state when lT(t) is included in the cover.

Example: Entrance Violations

Figure

Setting Up the Covering Problem

  • Since inclusion of certain context signals cause some states to have entrance violations, the covering problem is binate.
  • There is a row in the constraint matrix for each violation and each violation that could arise from a context signal choice.
  • There is a column for each context signal.
  • The entry in the matrix contains a 1 if the context signal excludes the violating state.
  • An entry in the matrix contains a 0 if the inclusion of the context signal would require a new violation to be resolved.
  • The constraint matrix for ER(c+,1) is shown below:

Example: Constraint Matrix

a
c
d
1100
1
-
-
1101
1
-
1
0110
0
1
-
1110
1
1
0

Example: Non-Persistent Trigger Signals
Figure

Example: Non-Persistent Trigger Signals
Figure

Example: Unresolvable Violations
Figure

Hazard-Free Decomposition

  • Synthesis method put no restrictions on the size of the gates.
  • There is always some limitation on the number of inputs.
  • In CMOS, no more than 4 transistors can be in series.
  • Large transistor stacks can have charge sharing problems.
  • Necessary to decompose high-fanin gates into limited-fanin gates.
  • For Huffman circuits, decomposition of high-fanin gates can be done in an arbitrary fashion preserving hazard-freedom.
  • For Muller circuits, this problem is much more difficult.

Example: Decomposition I

Figure Figure

Example: Decomposition II

Figure Figure

Hazard-Free Decomposition Overview

  • Special care needed to guarantee a hazard-free decomposition.
  • Need to find new internal signal that produces simpler circuit.
  • Present here a simple technique for finding hazard-free decompositions using insertion points.

Example: Insertion Points

Figure Figure

Example: Insertion Points

Figure Figure

Transition Point Filters

  • Requirements on transition points (ts,te):

    1. The start and end sets should be disjoint.
      (i.e., ts te = )
    2. The end set should not include input transitions.
      (i.e., "t te .  t \not TI)
    3. Start and end sets should only include concurrent transitions.
      (i.e., "t1, t2 ts .   t1 ||t2 and "t1, t2 te .   t1 ||t2)

Transition Point Filters for Decomposition

  • Consider decomposition of C(u*,k) composed of a single cube.
  • Restrict the start set for one transition point to transitions on just those signals in the gate being decomposed.

    • Consider all possible combinations of the trigger signals.
    • Only consider concurrent subsets of the context signals.

  • Only consider transitions that occur after those in the start set and before u* as potential candidates to be in the end set.

Transition Point Filters for Decomposition

  • If both a set region and a reset region of u must be decomposed, use same restrictions for the reverse transition on the new signal.
  • If not:

    • Start set should include concurrent transitions which occur after u* and before any transitions in the first start set.
    • Including the reverse transition of u* in the end set is often useful, but any transition after u* could be used.

Passive/Active Shop: gC Circuit

Figure

Rising Transition Point Choices

({ CSC0- }, { ack_wine+ })
({ req_patron- }, { ack_wine+ })
({ req_wine+ }, { ack_wine+ })
({ ack_patron- }, { ack_wine+ })
({ req_wine+, ack_patron- }, { ack_wine+ })

Falling Transition Point Choices

({ ack_wine+ }, { CSC0+ })
({ ack_wine+ }, { ack_wine- })
({ CSC0+ }, { ack_wine- })
({ req_wine- }, { CSC0+ })
({ req_wine- }, { ack_wine- })
({ CSC0+, req_wine- }, { ack_wine- })

Checking the Insertion Points

  • Form insertion points out of combinations.
  • Color the graph to determine if the insertion point leads to a consistent state assignment.
  • Check if any USC violations become CSC violations.
  • If okay, derive a new state graph and synthesize the circuit.
  • If new circuit meets the fanin constraints, then accept.
  • If not, try the next insertion point.

({ req_patron- }, { ack_wine+ })
({ ack_wine+ }, { ack_wine- })

Summary

  • Formal definition of speed independence.
  • State graph model.
  • Complete state coding.
  • Hazard-free logic synthesis of Muller circuits.
  • Hazard-free decomposition.


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On 2 Apr 2000, 20:48.