plain CS/EE 5750/6750: Asynchronous Circuit Design

CS/EE 5750/6750: Asynchronous Circuit Design

Chris J. Myers
Lecture 1: Introduction
Preface and Chapter 1

Course Information

Prerequisites

Textbook

  • Being written by me during the course.
  • Book available from the website.
  • Need to request an account on our website.
  • Will be updated every Monday morning.
  • Please report errors in the text.
  • Preface, chapter 1, and chapter 2 complete.

Grading policy

  • Homework - 40 percent
  • Project report - 40 percent
  • Oral presentation - 20 percent

Project

  • Major emphasis of course is on the final project.
  • Project types:

    • Solve a theoretical or algorithmic problem.
    • Implement a small CAD tool.
    • Design a small circuit.

  • Present in written report and oral presentation.

CS/EE 6750

  • Must complete extra homework problems.
  • Project must be more extensive.

Synchronous Systems

  • All events are synchronized to a single global clock.

Figure
Synchronous Advantages

  • Simple way to implement sequencing.
  • Widely taught and understood.
  • Available components.
  • Simple way to deal with noise and hazards.

Synchronous Disadvantages

  • Clock distribution is difficult due to clock skew.
  • Worst-case design.
  • Sensitive to variations in physical parameters.
  • Not modular.
  • Power consumption.

Asynchronous Systems

  • Synchronization is achieved without a global clock.

Figure
Asynchronous Advantages

  • Elimination of clock distribution problems.
  • Average-case performance.
  • Adaptivity to processing and environmental variations.
  • Component modularity.
  • Lower system power requirements.

Asynchronous Challenges

  • Lack of mature computer-aided design tools.
  • Large area overhead for the removal of hazards.
  • Average-case delay can be large.
  • Lack of designer experience.

Asynchronous Circuit History

  • Every asynchronous design method traces its roots to one of two key individuals:

    • Huffman - fundamental-mode circuits.
    • Muller - speed-independent circuits.

Key Asynchronous Circuit Designs

  • ILLIAC (1952) and ILLAC2 (1962) - U. of Illinois
  • Atlas (1962) and MU-5 (1966) - U. of Manchester
  • Macromodules (60s-70s) - Washington U., St. Louis
  • First commercial graphics system (70s) - Evans & Sutherland
  • DDM dataflow computer (1978) - U. of Utah
  • First asynchronous microprocessor (1989) - Caltech
  • First code-compatible processor (1994) - U. of Manchester
  • Commercial pager (90s) - Phillips
  • RAPPID (1995-9) - Intel

Wine Shop Problem Specification

  • Small winery and wine shop in Southern Utah.
  • Only a single wine patron.
  • Wine shop only has a single small shelf.
  • Synchronous versus asynchronous wine shopping.

Channels of Communication

Figure

Channels of Communication in VHDL

Winery:process
begin
     send(WineryShop,bottle);
end process;
Shop:process
begin
     receive(WineryShop,bottle);
     send(ShopPatron,bottle);
end process;
Patron:process
begin
     receive(ShopPatron,bottle);
end process;

Event Protocol

Shop:process
begin
     req_wine   -- call winery
     ack_wine   -- wine arrives
     req_patron -- call patron
     ack_patron -- patron buys wine
end process;

Signal Protocol

Shop:process
begin
     req_wine <= '1';             -- call winery
     wait until ack_wine = '1';   -- wine arrives
     req_patron <= '1';           -- call patron
     wait until ack_patron = '1'; -- patron buys wine
end process;

2-Phase Protocol

Shop_2Phase:process
begin
     req_wine <= '1';             -- call winery
     wait until ack_wine = '1';   -- wine arrives
     req_patron <= '1';           -- call patron
     wait until ack_patron = '1'; -- patron buys wine
     req_wine <= '0';             -- call winery
     wait until ack_wine = '0';   -- wine arrives
     req_patron <= '0';           -- call patron
     wait until ack_patron = '0'; -- patron buys wine
end process;

4-Phase Protocol: Active/Active

Shop_4Phase:process
begin
     req_wine <= '1';             -- call winery
     wait until ack_wine = '1';   -- wine arrives
     req_wine <= '0';             -- reset req_wine 
     wait until ack_wine = '0';   -- ack_wine resets
     req_patron <= '1';           -- call patron
     wait until ack_patron = '1'; -- patron buys wine
     req_patron <= '0';           -- reset req_patron 
     wait until ack_patron = '0'; -- ack_patron resets
end process;

4-Phase Protocol: Passive/Active

Shop_PA:process
begin
     wait until req_wine = '1';   -- winery calls 
     ack_wine <= '1';             -- wine is received
     wait until req_wine = '0';   -- req_wine resets
     ack_wine <= '0';             -- reset ack_wine 
     req_patron <= '1';           -- call patron
     wait until ack_patron = '1'; -- patron buys wine
     req_patron <= '0';           -- reset req_patron 
     wait until ack_patron = '0'; -- ack_patron resets
end process;

4-Phase Protocol: Passive/Passive

Shop_PP:process
begin
     wait until req_wine = '1';   -- winery calls 
     ack_wine <= '1';             -- wine is received
     wait until req_wine = '0';   -- req_wine resets
     ack_wine <= '0';             -- reset ack_wine
     wait until req_patron = '1'; -- patron calls 
     ack_patron <= '1';           -- shopkeeper sells wine
     wait until req_patron = '0'; -- req_patron resets
     ack_patron <= '0';           -- reset ack_patron 
end process;

4-Phase Protocol: Active/Passive

Active/Active Reshuffled

Shop_AA_reshuffled:process
begin
     req_wine <= '1';             -- call winery
     wait until ack_wine = '1';   -- wine arrives
     req_patron <= '1';           -- call patron
     wait until ack_patron = '1'; -- patron buys wine
     req_wine <= '0';             -- reset req_wine
     wait until ack_wine = '0';   -- ack_wine resets
     req_patron <= '0';           -- reset req_patron
     wait until ack_patron = '0'; -- ack_patron resets
end process;

Active/Active Circuit

Figure

Passive/Active Reshuffled

Shop_PA_reshuffled:process
begin
     req_wine <= '1';             -- call winery
     wait until ack_wine = '1';   -- wine arrives
     req_patron <= '1';           -- call patron
     wait until ack_patron = '1'; -- patron buys wine
     req_wine <= '0';             -- reset req_wine
     wait until ack_wine = '0';   -- ack_wine resets
     req_patron <= '0';           -- reset req_patron
     wait until ack_patron = '0'; -- ack_patron resets
end process;

Passive/Active Circuit

Figure

AFSM and Huffman Flow Table (A/A reshuffled)

Figure
00 01 11 10
0 1, 10 0(-3,3) , 00 - -
1 1(-3,3) , 10 - - 2, 11
2 - - 3, 01 2(-3,3) , 11
3 - 0, 00 3(-3,3) , 01 -

Petri-net (P/A reshuffled)

Figure

TEL Structure (P/A reshuffled)

Figure

A/A Reshuffled Circuit

Figure

P/A Reshuffled Circuit

Figure

Active/Active State Variable

Shop_AA_state_variable:process
begin
     req_wine <= '1';             -- call winery
     wait until ack_wine = '1';   -- wine arrives
     x <= '1';			  -- set state variable
     req_wine <= '0';             -- reset req_wine
     wait until ack_wine = '0';   -- ack_wine resets
     req_patron <= '1';           -- call patron
     wait until ack_patron = '1'; -- patron buys wine
     x <= '0';			  -- reset state variable
     req_patron <= '0';           -- reset req_patron 
     wait until ack_patron = '0'; -- ack_patron resets
end process;

A/A SV Circuit

Figure

AFSM and Huffman Flow Table (A/A SV)

Figure
00 01 11 10
0 1, -0 0(-3,3) , 00 - -
1 1(-3,3) , 10 - - 2, -0
2 3, 0- - - 2(-3,3) , 00
3 3(-3,3), 01 0, 0- - -

Reduced AFSM and Huffman Flow Table (A/A SV)

Figure
00 01 11 10
0 0(-3,3) , 10 0(-3,3) , 00 - 1, -0
1 1(-3,3), 01 0, 0- - 1(-3,3) , 00

Karnaugh Maps for Huffman's A/A SV Circuit

ack_wine/ack_patron ack_wine/ack_patron
x 00 01 11 10
0 1(-16,2)(45,10)[r] 0 - -(10,2)(45,10)[l]
1 0 0 - 0
x 00 01 11 10
0 0 0 - 0
1 1(8,2)(40,10) - - 0
req_wine req_patron

ack_wine/ack_patron
x 00 01 11 10
0 0 0 - 1
1 1(-16,2)(45,10)[r] 0 -(7,10)(40,33) 1(10,2)(45,10)[l]

x

Huffman's A/A SV Circuit

Figure

Huffman's Assumptions

  • Bounded gate and wire delay model.
  • Circuit does not need to be closed.
  • Single-input change fundamental mode.
  • One input changes output changes state changes.
  • May need to add delay in fed back state variables.

Muller's Active/Active SV Circuit

Figure

Muller's Assumptions

  • Unbounded gate delay model.
  • Wire delays are assumed to be negligible.
  • Forks are assumed to be isochronic.
  • Model called speed-independent.

Timed Wine Shop

Shop_AA_timed:process
begin
     req_wine <= '1' after delay(0,1);   -- call winery
     req_patron <= '1' after delay(0,1); -- call patron
     wait until ack_wine = '1' and ack_patron = '1';   
          -- wine arrives and patron arrives
     req_wine <= '0' after delay(0,1);  --reset req_wine
     req_patron <= '0' after delay(0,1);--reset req_patron
     wait until ack_wine = '0' and ack_patron = '0';   
          -- wait for ack_wine and ack_patron to reset
end process;

Timed Winery and Patron

winery:process
begin
     wait until req_wine = '1';	        -- wine requested
     ack_wine <= '1' after delay(2,3);  -- deliver wine
     wait until req_wine = '0';         -- req_wine reset
     ack_wine <= '0' after delay(2,3);  -- reset ack_wine
end process;
patron:process
begin
     wait until req_patron = '1';          -- shop called
     ack_patron <= '1' after delay(5,inf); -- buy wine
     wait until req_patron = '0';        -- req_patron reset
     ack_patron <= '0' after delay(5,7); -- reset ack_patron
end process;

TEL Structure for Timed Wine Shop Example

Figure

State Graph for Timed Wine Shop Example

Figure

Karnaugh Maps for Timed Circuit

ack_wine/ack_patron ack_wine/ack_patron
req_wine/
req_patron
00 01 11 10
00 1 0 0 -
01 - - 0 -
11 1 - 0 1
10 1 - - -
(-86,-6)(40,65)[r] (2,-6)(42,65)[l]
00 01 11 10
00 0 0 0 -
01 - - 0 -
11 1 - 1 1
10 1 - - -(-36,12)(82,30)
req_wine req_patron

Timed Circuit

Figure

Performance Analysis

  • Cycle time is the delay from when the patron gets one bottle of wine until he can get another.
  • Assuming the timed circuit delays are uniformly distributed except that the patron is extremely unlikely to take more then 10 minutes, we obtain the following cycle times:

    • Muller and Huffman's circuits (A/A SV) - 21.5 minutes
    • Original (A/A reshuffled) - 20.6 minutes
    • Timed circuit - 15.8 minutes

Validation versus Verification

  • Validation is simulation of interesting situations.
  • Verification is exhaustive checks of all possible situations.

    • Can check that circuit conforms to the specification.
    • Can check that protocol has certain properties (i.e., model checking).

Sample Properties

  • The wine arrives before the patron:

    • Always(ack_patron ack_wine)

  • When the wine is requested, it eventually arrives:

    • req_wine Eventually(ack_wine)

Summary of Course Topics

  • Communication Channels
  • Communication Protocols
  • Graphical Specifications
  • Huffman Style Synthesis
  • Muller Style Synthesis
  • Timing Analysis and Optimization
  • Performance Analysis and Verification


File translated from TEX by TTH, version 2.22.
On 11 Jan 2000, 16:39.