CS/EE 5750/6750 Handout #7
A brief project proposal is due by 3pm on Wednesday, March 8, 2000.
Please send it as plain text (not as attachment) by email to:
Feel free to come up with your own idea. The ideas below are only
CS/EE 5750 students:
CS/EE 6750 students:
- Design a small asynchronous circuit:
- Write and simulate a channel-level specification.
- Derive and simulate a handshaking-level specification.
- Synthesize a Huffman circuit.
- Synthesize a Muller circuit.
- Synthesize a timed circuit.
- Compare the results.
- Possible designs include but are not limited to:
- Any part of a microprocessor
- Decoder for an error correcting code
- Write a translator from channel-level VHDL to handshaking-level VHDL.
- Automate search of possible reshufflings at handshaking-level.
- Write a translator from handshaking-level to a graphical representation.
- Implement a tool for state minimization of Huffman circuits.
- Implement a tool for state assignment of Huffman circuits.
- Implement a tool for multi-level logic synthesis of Huffman circuits.
- Implement a tool for technology mapping of Huffman circuits.
- Implement a tool for state assignment of Muller circuits.
- Implement a tool for technology mapping of Muller circuits.
- Implement a tool for state assignment of timed circuits.
- Implement a tool for technology mapping of timed circuits.
- Implement a performance analysis tool for asynchronous circuits.
- Implement a translator from TEL structures to timed automata
and use a timed automata tool for verification.
- Write a translater from an asynchronous specification to a
model-checking verification tool's input form, such as SMV.
- Design and simulate at the circuit-level a small system which has
the potential for a performance or power improvement over
synchronous design. Design should begin at channel level and go
all the way down to transistors. Perform a comparison with a
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On 4 Mar 2000, 18:33.