CS/EE 5750/6750 Handout #11
Spring 99-00


This homework is due electronically by midnight on Friday, April 14th, 2000.

In this assignment, you will learn how to use the ATACS tool for logic synthesis.

  1. Go to following web address and download all listed files:
    www.async.elen.utah.edu/ ~ myers/book/tool/

  2. Be sure to put the atacs.exe files and dll's in the same directory.

  3. Create a new project called tutorial in VeriBest and add the vhdl files included on this website. Simulate the design. Be sure to add nondeterminism.vhd and handshake.vhd.

  4. Select Tools Customize menu entry.

  5. In the new window, select the Tools tab.

  6. Select Add and enter the following:

  7. Select Redirect Output and click OK.

  8. Right click on ShopAP and select Open.

  9. Select Tools ATACS-SI.

  10. You should see output at bottom of screen ending with a statement that it generated VHDL.

  11. Select Project Add to Project Add Design File.

  12. Browse to vbproj/tutorial/design_definition/hdl/vhdl where you should find a file ShopAPS.vhd, and select it. Select copy and ignore the error that files are the same.

  13. Right click on ShopAP and select Properties, click on the Settings tab and click on the pulldown menu to find the file ShopAPS, and select it.

  14. You should now, see a + next to ShopAP. Expand it and you will see a number of files that are missing. They have names like n3p2. Use the Add Design File command to add them.

  15. Simulate your structural design, and
    email: myers@vlsigroup.elen.utah.edu your file ShopAPS.vhd.

  16. CS/EE 6750 and extra credit for CS/EE 5750
    Assume that you are only allowed 2-input gates. This design requires two 3-input gates initially. Using the attached state graph, find an insertion point for the signals y and z which leads to a design using only 2-input gates.
    Email: myers@vlsigroup.elen.utah.edu your new ShopAP.vhd file.


File translated from TEX by TTH, version 2.22.
On 8 Apr 2000, 21:55.