CS/EE 5750/6750 Handout #1
Spring 99-00
Myers

CS/EE 5750/6750: Asynchronous Circuit Design



Chris J. Myers

Course description

In recent years, there has been a resurgence of interest in the design of asynchronous circuits due to their ability to eliminate clock skew problems, achieve average case performance, adapt to environmental and processing variations, provide component modularity, and lower system power requirements. There is, however, a widely held belief that asynchronous design is difficult and leads to inefficient and unreliable designs. The goal of this course is to dispel this belief by introducing a systematic approach to the design of asynchronous VLSI systems from a high-level specification to an efficient and reliable circuit implementation. This course will include both hands-on experience with existing CAD tools as well as learn the algorithms within them. There will be weekly homeworks and a final project. Topics will include: specification, synthesis, optimization with timing information, performance analysis, and verification.

Prerequisites

Students should have a familiarity with computer programming (CS 2010-2020), digital logic design (CS/EE 3700), and algorithms and data structures (CS 3510). Courses in computer organization (CS/EE 3810 and CS/EE 3710) and integrated circuit design (CS/EE 5710-5720) are recommended.

Textbook

The textbook is being written by me during the course. It will be available from the course website.

Grading policy and Project

Homework 40 percent
Project Report 40 percent
Oral Presentation 20 percent

The major emphasis of this course will be on the final project. Students will choose between many different types of projects including investigating some theoretical or algorithmic problem, writing a small CAD tool, or designing a small circuit. Each student must present the project both in a written report and a 15 minute oral presentation.

CS/EE 6750

Students taking CS/EE 6750 will be expected to solve extra homework problems and complete a more extensive project.

Course Info

COURSE:
Credits:
Place:
Time:
Class email:
Class webpage: CS/EE 5750/6750
3
TBD
TBD
ee5750@vlsigroup.elen.utah.edu
http://www.async.elen.utah.edu/ ~ myers/ee5750/

INSTRUCTOR:
Electronic Mail:
Location:
Telephone:
Office Hours: Chris J. Myers
myers@vlsigroup.elen.utah.edu
MEB 4112
581-6490
TBA

Extended TENTATIVE Syllabus

  1. Introduction to asynchronous circuit design
  2. Communication channels

    • Modeling asychronous communication in VHDL
    • Example: MiniMIPS

  3. Communication protocols

    • Process decomposition
    • Control protocols
    • Data encoding
    • Syntax-directed translation

  4. Graphical specification

    • Asynchronous finite state machines
    • Petri-nets
    • Timed event/level structures

  5. Huffman style synthesis

    • State minimization
    • State assignment
    • Hazard-free logic synthesis

  6. Muller style synthesis

    • State space exploration
    • Complete state coding
    • Hazard-free logic synthesis
    • Technology mapping

  7. Timing analysis and optimization

    • Introduction to timed circuits
    • Finding time differences
    • Timed state space exploration

  8. Performance analysis and verification

    • Performance analysis
    • Conformance checking
    • Model checking


File translated from TEX by TTH, version 2.22.
On 11 Jan 2000, 16:31.