That is a great idea


Re:
Re:Re:Re:Synthesis Problems -- Chris Myers
Posted by Jas , May 09,1999,17:36 Post Reply  Forum

That was exactly what I was going to suggest. Set the input to the gate as a pin on the Xilinx and the rest of the clocks to the standard pin 13 (TA's can clarify if you don't understand).
The only other thing I thought would help you is one of the TA boards does this. Board #1 has pin 13, 7, and 38 tied to the clock (only on board #1 to my knowledge). Pin 13 is the standard clock, so you can choose 7 or 38 to your discretion. (These are Xilinx pins, not bus pin numbers).

Good luck!

Copied from a previous post:

BOARD #1:
---------
Pins | Edge connecter | Xilinx pins
Acc7 , G , 50
Acc6 , H , 51
Acc5 , I , 52
Acc4 , J , 53
Acc3 , C , 46
Acc2 , D , 47
Acc1 , E , 48
Acc0 , F , 49

Addr7, 5 , 14
Addr6, 6 , 15
Addr5, 7 , 16
Addr4, 8 , 17
Addr3, 9 , 18
Addr2, 10 , 19
Addr1, 11 , 20
Addr0, 12 , 23

Data7, 13 24
Data6, 14 25
Data5, 15 26
Data4, 16 27
Data3, 17 28
Data2, 18 29
Data1, 19 30
Data0, 20 35

Reset, 26 45

Clk , 4 13