Re:Re:Re:Synthesis Problems


Re:
Re:Re:Synthesis Problems -- Chris Winstead
Posted by Chris Myers , May 08,1999,13:10 Post Reply  Forum

The easiest solution is to run the clock into the Xilinx FPGA through
two pins. In other words, the clock signal is run to the latch clock
inputs from pin 13. The clock running in from another pin can be run
to logic.

If you need the output of the logic to go to the latch clock input,
I don't believe you can do this. The issue is that pin 13 is physically
routed in the FPGA to the latch clock input and cannot be changed.

The only way around this that I can think of off hand is to build a
latch out of combinational logic and route the gated clock input to
that latch. This is obviously a pretty obnoxious work around, so
it may be better to see if there is anyway to pull the logic off
chip. If you do this, then you can route the gated clock input in
from another pin (i.e., not pin 13). This is actually your best bet.


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