If you need the output of the logic to go to the latch clock input,
I don't believe you can do this. The issue is that pin 13 is physically
routed in the FPGA to the latch clock input and cannot be changed.
The only way around this that I can think of off hand is to build a
latch out of combinational logic and route the gated clock input to
that latch. This is obviously a pretty obnoxious work around, so
it may be better to see if there is anyway to pull the logic off
chip. If you do this, then you can route the gated clock input in
from another pin (i.e., not pin 13). This is actually your best bet.