Re:Re:Synthesis Problems

Re:Synthesis Problems -- Jas
Posted by Chris Winstead , May 08,1999,10:45 Post Reply  Forum

There is at least one point in the design where the clock is tied to a gate input. This is not avoidable in our design, so if this is the cause of the error we will need to find some way around it. Did you (Jas) mention that you knew a solution?
The full text of the error message was not available to my partner when the post was written, hence the "blah blah blah" portions. I can provide more details in a later post...