My design simulates but doesn't work in Xilinx.

Posted by egm , May 07,1999,18:27 Post Reply  Forum

The problem you are experiencing could be related to a bus labeling issue. In the simulator, Veribest is able to match high order bits to high order bits. This means that if you label all of your buses A[0:7], the simulator is smart enough to map you high order A(0) bit to my high order A(7) bit. However, this does NOT work in synthesis. The synthesis engine maps your A(0) to my A(0)... your A(7) to my A(7). This means that you think you are sending memory address 0000 0001 but memory sees address 1000 0000. This makes it seem as though your design is not working. Any where you use a [0:7] labeling, you need to change to [7:0] for it to work correctly in synthesis with our test board.