A few of my thoughts.
Re: Because nobody answered my post so I'll post it again! Error] Illegal port map -- Irrelevant
1) Try and run tools->Generate HDL.
2) Make sure that the AND2B1 simbol in the hierarchy window in Veribest
has a big blas "M" on it.
3) Delate all of the generated VHDL code from the project directory.
Have you changed any properties on the AND3B1 symbol?
Try removing every istance of AND2B1 from you project, remove the associated files from the project, and then readd it into the project.