Isn't this project a bit unfair?

Posted by CS , May 04,1999,16:54 Post Reply  Forum

At the risk of sounding like a whiner, not something I typically consider myself, I would like to post for the class's consideration (and response) this question: isn't this project unfair to those of us who didn't get to check out working XILINX boards? People with the right XILINX chip could do all their wiring on their own, and debug it and spend as much time as they wanted working on it. The rest of us have to take our boards, wired to use the bus, to the lab when a TA is there, wait for him to find time for us, and then we get 60 seconds to plug our EPROM in and see if the whole messy configuration (the bus, the two EPROMs, our wiring job, the TA's wiring job) all somehow miraculously work together correctly. And if it doesn't work? (And logically this seems like the more likely outcome...) Well then, the TA takes his board back, and you're left to check your own wiring over a second time, and wonder why the design that simulated perfectly is not working at all. Without a chance to check out what's going into, and coming out of, the XILINX chip there's no way to get any idea of what's actually happening to keep the thing from working. Does this inability to troubleshoot strike anyone else as unfair?

Supposedly there is now the option of programming the XILINX chip to work with just the wiring on the TA's board and not do any wiring of your own. However, I haven't seen anything that specifies what XILINX pins to use. Is this available somewhere? I've looked over the web page and it doesn't seem to be anywhere (unless it was added to the zipped project file, but there is no mention of that on the web board.) And once again, even if we change or pins to match and reprogram the EPROM, if we run into a problem when checking off there still won't be any opportunity for debugging.

It's unfortunate that we've all been forced to be part of this "wonderful" change to semesters this year. The pitfalls of being in this newly reorganized EE class are just one of the joys I've experienced as a result, and I'm sure some of you have other, better anecdotes that you could share on this topic. It's a bit late for major changes to be made to this project, either in the grading or in the way that the project is supposed to be done. However, since changes have been made to the project (we can now use the TA's board for checking off and don't have to do any wiring of our own) I would like to propose that changes also be made to the grading standard.

To level the playing field for all of us, I suggest that the grades be based on everything up to and including the state machine simulation. We've all had access to the NT lab and the same software and could have reached that point. However, since we don't all have access to the same hardware I suggest that the wiring/implementation portion of the project be changed to credit/no-credit or else give extra-credit to those students who succesfully implemented their "computer".

Let me, and the "powers that be", know what you think. If you have an opinion, please post a response.

Yours Truly,

A Concerned Student