Help with compiling in simulator

Posted by Mark , May 03,1999,13:43 Post Reply  Forum

I am tring to compile our project in the simulator. It works fine until it tries to compile the classio.vhd file. At that point it gives the following error

vc comp -uns_vis -k87 U:\cs3700\project\EPROM\classio.vhd
VeriBest VHDL Compiler -

Compiling Package Declaration CLASSIO
Compiling Package Body CLASSIO

61: case;
[Failure] Syntax error : received 'case'
while expecting COMMENT
or 'architecture' or 'configuration' or 'entity' or 'library'
or 'package' or 'use'


I am not exactly sure what this is trying to tell me or how to fix it. I have got the newest project essesntials files from the web page.

Any help would be greatly appreciated...