Sounds like a problem in the design or the drawn logic.


Re:
Timing?? -- 7
Posted by egm , May 03,1999,07:37 Post Reply  Forum

Do the outputs from the implemented state-machine match the outputs from your paper design? Is your implemented state-machine doing exactly what your paper designs was intended to do? If your implemented machine matches your paper machine, then you can conclude that your design is not correct. If it doesn't match, then you must have an error in your logic. From your description, it sound like AccLoad, PCInc, and MBRLoad are not being asserted in the correct states.