EE/CS 3700

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Is anyone here? --- Tiny Tim ( Wed, Jun 23, 1999, 22:39:44 ) ( 5 bytes )
TA boards sat/sun? --- jon ( Fri, May 07, 1999, 19:40:48 ) ( 117 bytes ) +1
Synthesis Problems --- John Broadhead ( Fri, May 07, 1999, 18:53:32 ) ( 613 bytes ) +1
My design simulates but doesn't work in Xilinx. --- egm ( Fri, May 07, 1999, 18:27:12 ) ( 711 bytes )
MONDAY DEMOS --- Chris Myers ( Fri, May 07, 1999, 09:50:26 ) ( 305 bytes )
Errors in Synthesis --- Frustrated ( Thu, May 06, 1999, 18:40:59 ) ( 201 bytes ) +1
************* munge update and added test program ************** --- egm ( Thu, May 06, 1999, 16:50:32 ) ( 243 bytes )
Re: Passing off --- Pack ( Thu, May 06, 1999, 16:11:04 ) ( 283 bytes ) +1
Spontaneous PC Reset --- Jon Willesen ( Thu, May 06, 1999, 16:08:29 ) ( 397 bytes ) +3
Clarification on Demo Boards --- Kip Killpack ( Thu, May 06, 1999, 12:42:49 ) ( 1688 bytes )
free logic probe --- borrower ( Thu, May 06, 1999, 12:13:13 ) ( 186 bytes )
Burning Problem --- Jack yong ( Thu, May 06, 1999, 00:30:57 ) ( 188 bytes ) +2
Will there be TAs available for checkoff on Friday? --- MiniKit Masta ( Wed, May 05, 1999, 23:36:00 ) ( 18 bytes ) +2
ADSU8:1 --- Frustrated ( Wed, May 05, 1999, 20:19:25 ) ( 130 bytes ) +1
  • Re:ADSU8:1 --- David Henderson ( Wed, May 05, 1999, 21:30:45 ) ( 154 bytes ) +1
    • Re:Re:ADSU8:1 --- MiniKit Masta ( Wed, May 05, 1999, 22:48:02 ) ( 756 bytes )
Pinouts to match the TA Board --- Shiv ( Wed, May 05, 1999, 14:41:05 ) ( 2240 bytes ) +2
Because nobody answered my post so I'll post it again! Error] Illegal port map --- Irrelevant ( Wed, May 05, 1999, 14:27:57 ) ( 677 bytes ) +2
Office hours --- Chris Myers ( Wed, May 05, 1999, 14:01:25 ) ( 333 bytes )
Hand in Documentation? --- Mono ( Tue, May 04, 1999, 21:40:55 ) ( 155 bytes ) +1
Vdd/Vpp/Vcc --- confused ( Tue, May 04, 1999, 19:53:13 ) ( 151 bytes ) +1
  • Re:Vdd/Vpp/Vcc --- Jas ( Tue, May 04, 1999, 21:02:57 ) ( 289 bytes ) +1
    • ? --- HelpSeeker ( Tue, May 04, 1999, 21:12:49 ) ( 175 bytes )
Borrowed logic probe --- borrower ( Tue, May 04, 1999, 18:39:14 ) ( 243 bytes )
Please Answer this question! --- Big $Money$ Otis ( Tue, May 04, 1999, 18:06:36 ) ( 207 bytes ) +1
Isn't this project a bit unfair? --- CS ( Tue, May 04, 1999, 16:55:03 ) ( 3119 bytes ) +2
pin assignment for xilinx --- annon ( Tue, May 04, 1999, 11:11:40 ) ( 178 bytes ) +2
EXTENSION TILL NOON MAY 10th --- Chris Myers ( Tue, May 04, 1999, 11:11:02 ) ( 565 bytes ) +1
Shooter --- Blake Nelson ( Tue, May 04, 1999, 09:15:54 ) ( 354 bytes ) +1
  • More Shooter --- Blake Nelson ( Tue, May 04, 1999, 09:56:45 ) ( 935 bytes ) +1
    • I feel stupid --- Blake Nelson ( Tue, May 04, 1999, 10:02:32 ) ( 190 bytes )
[Error] Illegal port map: component AND2B1 does not have ports ?? --- Irrelevant ( Tue, May 04, 1999, 09:04:01 ) ( 717 bytes )
Counter CB8CLE --- HelpSeeker ( Tue, May 04, 1999, 05:40:34 ) ( 137 bytes ) +1
Things were going fine and then: --- Maury Hill ( Mon, May 03, 1999, 20:36:36 ) ( 988 bytes )
Pin names in synthesis --- Jesse Hall ( Mon, May 03, 1999, 18:31:45 ) ( 615 bytes )
Final Grades --- Anxious Student ( Mon, May 03, 1999, 13:58:44 ) ( 107 bytes ) +1
Help with compiling in simulator --- Mark ( Mon, May 03, 1999, 13:43:44 ) ( 829 bytes ) +3
Error in simulation --- Big H ( Mon, May 03, 1999, 11:31:21 ) ( 422 bytes )
Missing pins (G,I,O) on wirewrap board --- Gordon Swenson ( Mon, May 03, 1999, 09:00:04 ) ( 332 bytes ) +1
Sounds like a problem in the design or the drawn logic. --- egm ( Mon, May 03, 1999, 07:37:09 ) ( 473 bytes )
Did you try the tools->generate HDL option. --- egm ( Mon, May 03, 1999, 07:30:49 ) ( 41 bytes )
The undefined memory address is a normal warning that everyone will get. --- egm ( Mon, May 03, 1999, 07:25:00 ) ( 430 bytes )
WRONG EPROM INFO! --- Steven Fambro ( Sun, May 02, 1999, 23:30:14 ) ( 1829 bytes ) +2
Synthesizing --- op ( Sun, May 02, 1999, 22:41:29 ) ( 202 bytes ) +1
Shooter problems --- Jesse Hall ( Sun, May 02, 1999, 21:22:57 ) ( 586 bytes )
Bus Assignment Problem --- Mono ( Sun, May 02, 1999, 17:54:00 ) ( 628 bytes ) +1
VeriBest and paths with spaces --- Maury Hill ( Sun, May 02, 1999, 16:43:16 ) ( 721 bytes ) +1
Assember errors --- Walter ( Sun, May 02, 1999, 14:07:28 ) ( 316 bytes ) +1
CDBC compiling errors in Simulator --- C. Crofts ( Sun, May 02, 1999, 13:03:05 ) ( 147 bytes ) +1
Re:Internal Flip Flop errors?? --- Chris Myers ( Sun, May 02, 1999, 10:06:35 ) ( 132 bytes )
Re:What is requisite in order to checkoff? --- Chris Myers ( Sun, May 02, 1999, 10:04:59 ) ( 182 bytes )
Re:error message --- Chris Myers ( Sun, May 02, 1999, 10:02:48 ) ( 299 bytes ) +1
Re:Set/reset net warning --- Chris Myers ( Sun, May 02, 1999, 09:59:06 ) ( 259 bytes )
Question: Tri-state XSIG --- HelpSeeker ( Sun, May 02, 1999, 05:46:10 ) ( 616 bytes ) +1
Important note about the ADSU8 .... --- IamAnon ( Sat, May 01, 1999, 22:34:08 ) ( 1447 bytes )
another ALU problem --- Chris Taylor ( Sat, May 01, 1999, 20:42:03 ) ( 1530 bytes ) +1
Use your own name! --- Maury Hill ( Sat, May 01, 1999, 20:27:11 ) ( 86 bytes )
Re:more on timing message --- IamAnon ( Sat, May 01, 1999, 20:17:59 ) ( 37 bytes )
Re:Timing?? --- IamAnon ( Sat, May 01, 1999, 20:16:02 ) ( 535 bytes ) +1
wire up and eprom --- J.L.P ( Sat, May 01, 1999, 19:42:23 ) ( 450 bytes ) +1
More EPROM questions. --- MD ( Sat, May 01, 1999, 18:46:23 ) ( 919 bytes ) +1
What do I do with a bad Xilinx Board? --- Mono ( Sat, May 01, 1999, 18:13:47 ) ( 928 bytes ) +1
Re:Waveforms won't print --- Mono ( Sat, May 01, 1999, 17:48:40 ) ( 360 bytes )
Re:EPROM Pinouts --- George ( Sat, May 01, 1999, 17:36:15 ) ( 173 bytes )

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