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Triscuit's Data Path

The data path of Triscuit is eight-bits wide and very simple. It basically consists of an eight-bit two's complement ALU that implements addition and subtraction (Remember Lab 6!), an eight-bit accumulator (register) to hold results, and registers to hold the current instruction and the PC. Note that because of the strange immediate addressing mode that Triscuit uses, the memory address will come either from the PC (to fetch the next instruction) or from the instruction register in the case of a STORE instruction (the data value in a STORE instruction is the address to store to). Realize that the address to store to is in the data stream, so the store address will be in the instruction register. You should be able to drive the memory address from either of these two places.

A possible block diagram of the data path of the Triscuit processor is shown in Figure 1. Note that the thick lines in the figure are buses. In this case, since the data path of Triscuit is eight bits wide, the buses in Figure 1 are all eight bits wide.

Figure 1: An Example Triscuit Data Path

First look at the top of Figure 1. This includes the ALU (actually just an adder/subtracter in this case), and the accumulator register. It also includes a zero detector that looks at the output of the accumulator. You should remember how to make a zero detector. The accumulator is an eight-bit edge-triggered D-type register with an enable signal and a clear. When the enable signal is asserted the register will load a new value into its flip flops on the next rising edge of the clock. In this case, the signal comes from the state machine and is called LD-ACC. An FD8CE or FD8RE from the xc3000 library might make good choices for this register.

The ALU is a simple adder-subtracter circuit. It behaves the same as your Lab6 adder, but doesn't have to be look-ahead or carry-select, it just needs to add and subtract. You could build your own, or you could just use one of the adder-subtracter circuits from the xc3000 library (like the ADSU8 for example). Note that the inputs to the ALU come from the data-in lines from memory, and also from the output of the accumulator. This means that everything that gets added or subtracted uses the current value in the accumulator as one of its arguments, and a data value from memory as the other argument. This is what is meant by ``accumulator machine.'' Note also that the output from the accumulator goes to the data-out lines which go back to the memory (actually just a set of lights in our case). This is because any data that Triscuit stores out to memory must come from the accumulator.

The three boxes on the bottom of Figure 1 contain the Instruction Register (IR), Program Counter (PC), and a MUX that is used to select which value is sent to the memory as the next address. The IR is just an eight bit latch the same as the accumulator. Note that it also is loaded when a signal comes from the state machine. The signal to load the IR is LD-INST and it works the same way as the LD-ACC does for the accumulator.

The PC is probably best implemented using a counter. A counter is simply a register with a built-in increment-by-one circuit so that is can either load a completely new value (when LOAD is asserted), or count up by one (when EN is asserted). Think of this a a register with one extra added feature (that it can increment its contents). In the xc3000 library you will find a variety of counters. A CB8CLE might be a good choice since it is eight-bits wide, has a clear, a load, and an enable signal.

Finally, you will need to choose whether the address to ``memory'' is coming from the PC or from the IR. Usually the PC is the right choice because you are either fetching a new instruction, or fetching the data that follows the instruction in the data stream. The STORE instruction is the weird one.

Consider how a store executes. First you fetch the STORE instruction itself. The state machine sees that it's a STORE and goes to a sequence of states to execute a STORE. The operation of the STORE is to take the data following the STORE instruction as the address to store to, and store the current contents of the accumulator to that address. So, the next thing you do is increment the PC and fetch the data for the STORE (which is the address to store to). This needs to be stored somewhere, so you can put it in the IR (after all, you already know you're doing a STORE so you don't necessarily need it sitting around any more. (Side note: you could, of course, have an additional register just to hold the store address that would be separate from the IR. That would work fine too if you're confused by using the IR for double-duty)

Now that you have the address to store to, and the data to store (sitting in the accumulator), you can change the MUX so that the address going to the ``memory'' is the store address instead of the PC (i.e. the state machine asserts the ADDR-SEL signal), and set a signal to the memory to signal that the operation is write rather than read (this signal comes from the state machine and is called RBAR-W because it is 0 when you are doing a read, and 1 when you are doing a write). This causes the store to happen. Now you can increment the PC to get the next instruction, switch the MUX back to sending the PC value to the ``memory'', and fetch the next instruction.

next up previous
Next: Triscuit's Control State Machine Up: No Title Previous: Decrement Until 0

Erik Brunvand
Sat Nov 29 15:21:21 MST 1997