Another interesting aspect of the FPGAs is that you can't really know the timing of the circuits until after it has gone through the place and route process. That's because you can't tell how much delay, loading, etc. there is on each gate until you know where these gates are placed on the chip. So, if you want to simulate your design with ``real'' timings (that is, estimates of the timing with the physical layout of the circuit taken into account), you need to run another step which is typically called back annotation. Back annotation is the process of annotating post-layout delays into the simulation file so that you can simulate again with more realistic delays in the simulation.
The program to run to back-annotate your design is in the /home/cs/handin/cs361/bin directory and is called xtiming. The interface is the same as for xxx. Connect to your cs361-pv/lab7 directory, and run:
This will run a whole bunch of Xilinx programs and end up overwriting your <xilinx-design-name>.vsm file with extra information about post-layout timing.