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Structuring Your Circuit

It is also essential that all the parts of the system that will be contained in the Xilinx part must be be rooted in a single top-level schematic that represents the Xilinx chip. Your Triscuit state machines will clearly be designed using good hierarchical structuring, but they should all be rooted in a common, top-level, ancestor schematic. You will make one symbol for the Xilinx part, and pushing into the schematics that are underneath that symbol, you should eventually get to all Xilinx-related circuits. Everything under that symbol will be in the Xilinx part, and anything not under that symbol will be wired from the other components in your kit.

Once you've decided which parts of the circuit will be contained in the Xilinx part, you need to specify which pins of the Xilinx part will be used for your signals. This is programmable like the rest of the Xilinx configuration. The Xilinx chip that is available in the lab is packaged in an 84pin PLCC package. Some of those pins are used for specific purposes, and others can be used for I/O for your design. The wires that come from your design and need to go off the Xilinx chip to the rest of the project must be connected through pad cells and buffers. You should use ibuf and ipad cells from the xc3000 library for any inputs to your project, and obuf and opad cells for any outputs from your design. For each ipad-ibuf and obuf-opad combination, you should give that pin a label so that you can remember what it is for. The thing that you label is the little piece of net between the pad and buffer.

The only addition to this rule is that the Xilinx part has a dedicated clock lines that are handy to use for your clock signal. To use the clock line, connect the clock signal to an ipad as usual, but instead of using an ibuf between the pad and the circuit, use a gclk buffer. This will indicate that the signal should use the global clock line. Also, this signal should be connected to pin 13 of the Xilinx part. The following paragraphs will tell you how to force a pad to a particular pin.

Once you have decided which signals are going on and off the Xilinx chip, you might ask how they get mapped to specific Xilinx pins? How do you know where to find those signals once the circuit is mapped to the Xilinx part? One answer is to let the Xilinx tools map the pins for you and then look them up afterwards in the output file from the place and route process. This is fine except that there are so many pins on the Xilinx part that have to be used in special ways, it might be better if you just avoided those pins to start with.

Another better technique for our purposes is to force the signals that you are interested in to specific pins in the first place. You can fix the signals to specific pins by adding attributes to the ipad and opad cells that tell the xilinx tools which pins to attach to. Add an attribute by selecting the pad cell and typing ctl-a (or use the menu with change tex2html_wrap_inline541 attribute tex2html_wrap_inline541 dialog tex2html_wrap_inline541 all). This will bring up a dialog box with all the attributes assigned to that pad (there should only be a couple there already). Add a LOC attribute by adding LOC to one of the lines on the left hand side, and the pin number that you want that signal to be assigned to on the line on the right hand side as Pnum. For example, if you want to assign a signal to pin 20 of the Xilinx chip, the value of the LOC attribute for that pad would be P20. This should show up on your screen as LOC=P20 in yellow just under the pad cell. Now, when you use the Xilinx tools, the place and router will force that signal onto that pin. Note that you can move the attribute around relative to the pin it is attached to by selecting the yellow text and moving it. This will probably make your schematic look much nicer.

The pins that you can use for your parts are as follows: the special clock input pin is pin 13, and the general I/O pins are pins 7, 13-20, 23-30, 35, 37-40, 44-53, 57, 59, 63, 69, and 79-80. There are 38 usable pins here which should be more than enough for this project.

At any stage along the way you can simulate the circuits that you are designing using viewsim the same way as you've always used it. Use vsm to create a .vsm file, and then run viewsim. The simulator knows how to handle the Xilinx parts.

As an example, look at the circuit in Figure 4. This circuit isn't directly related to any of the pieces of your Triscuit (in fact, it's an example from last year's UART), but it does show how a circuit (encapsulated in a symbol) might be connected to pads on the Xilinx chip. All inputs have an IPAD and an IBUF before the input gets to the circuit, and all outputs have an OBUF and then an OPAD before they are seen by the outside world. The IPAD and OPAD represent the actual bonding pads on the Xilinx chip and therefore represent the actual pins on the chip. The IBUF and OBUF represent internal buffers on the Xilinx chip that are used to drive the external signals in and out of the Xilinx chip. Each input and output needs these things! Also notice that the label for that signal goes on the little stub of net that is between the PAD and BUF. Note that the clock signal has been assigned to pin13 and is coming in through a gclk buffer rather than an ibuf buffer. The other inputs use ibuf buffers and the outputs use obuf buffers. All the pins have been assigned using LOC attributes and all the signals have been named by naming the wire between the buffer and pad. The LOC attributes are attributes of the PAD symbols.

Figure 4: Example using Xilinx Pads

In order to simulate your entire system, including the switches and lights, you should make a symbol for the xilinx-schematic (the one with the pad cells in it). This symbol can then be included in your top-level schematic (your top-level schematic is the one that has your switches and lights in it).

next up previous
Next: Partitioning Across Multiple Boards Up: No Title Previous: Using the Xilinx Parts

Erik Brunvand
Sat Nov 29 15:21:21 MST 1997