Chris J. Myers
Chris J. Myers
Professor of Electrical and Computer Engineering
Adjunct Professor of Computer Science
Adjunct Professor of Bioengineering
4112 Merrill Engineering Building
(801) 581-6490
(801) 581-5281 (fax)
myers (email: add ece DOT utah DOT edu)
Education
Ph.D., Electrical Engineering,
Stanford University, 1995
M.S., Electrical Engineering,
Stanford University, 1993
B.S., Electrical Engineering and Chinese History,
Caltech, 1991
Research Interests
My current research interests are algorithms for the computer-aided analysis
and design of real-time concurrent systems, analog error control decoders,
formal verification, asynchronous circuit design, and modeling, analysis, and
design of genetic circuits.
For a complete description of our group's research activities, please
see our web site at
www.async.ece.utah.edu.
Selected Publications
- C. J. Myers, Engineering
Genetic Circuits, Chapman & Hall/CRC Press, July 2009.
- C. J. Myers, Asynchronous
Circuit Design, John Wiley and Sons, July 2001.
- C. J. Myers (translated by T. Yoneda), Asynchronous Circuit Design
(in Japanese), Kyoritsu Shuppan, September, 2003.
- C. Myers, N. Barker, K. Jones, H. Kuwahara, C. Madsen, and N. Nguyen,
"iBioSim: a tool for the analysis and design of genetic circuits," to appear
in Bioinformatics.
- N. Barker, C. Myers, and H. Kuwahara, "Learning genetic regulatory network
connectivity from time series data," to appear in IEEE Transactions on
Computational Biology and Bioinformatics.
- D. Walter, S. Little, C. Myers, N. Seegmiller, and T. Yoneda,
"Verification of analog/mixed-signal circuits using symbolic methods,"
in IEEE Transactions on CAD, 27(12): 2223-2235, December, 2008.
- H. Kuwahara and C. Myers,
"Production-Passage-Time Approximation: A New Approximation Method to Accelerate the Simulation Process of Enzymatic Reactions" in Journal of
Computational Biology, 15(7): 779-792, September, 2008.
- T. Yoneda and C. Myers, "Synthesis of timed circuits based on
decomposition", in IEEE Transactions on CAD, 26(7): 1177-1195, July, 2007.
- C. Nelson, C. Myers, and T. Yoneda, "Efficient verification of
hazard-freedom in gate-level timed asynchronous circuits",
in IEEE Transactions on CAD, 26(3): 592-605, March, 2007.
- H. Kuwahara, C. Myers, N. Barker, M. Samoilov, and A. Arkin,
"Automated abstraction methodology for genetic regulatory networks",
in Transactions on Computational Systems Biology VI, LNBI 4220, 150-175,
2006 (Invited Paper).
- H. Zheng, C. Myers, D. Walter, S. Little, and T. Yoneda,
"Verification of timed circuits with failure directed abstractions",
in IEEE Transactions on CAD, 25(3): 403-412, March, 2006.
- C. Winstead, J. Dai, S. Yu, C. Myers, R. Harrison, C. Schlegel,
"CMOS analog MAP decoder for (8,4) Hamming Code, in Journal of Solid State
Circuits", 39(1), 122-131, January, 2004.
- H. Zheng, E. Mercer, and Chris J. Myers,
"Modular verification of timed circuits using automatic abstraction",
in IEEE Transactions on CAD, 22(9), September, 2003.
- H. Jacobson and C. J. Myers,
"Efficient algorithms for exact two-level hazard-free logic minimization",
in IEEE Transactions on CAD, 21(11): 1269-1283 (Best Paper Finalist ASYNC01).
- S.-T. Jung and C. J. Myers,
"Direct synthesis of timed circuits from free-choice STGs",
in IEEE Transactions on CAD, 21(3): 275-290, March, 2002.
- K. Stevens, S. Rotem, R. Ginosar, P. A. Beerel, C. J. Myers, K. Yun,
R. Kol, C. Dike, and M. Roncken,
"An Asynchronous Instruction Length Decoder",
in IEEE Journal of Solid State Circuits, 36(2): 217-228, February, 2001
(Best Paper ASYNC99).
- W. Belluomini and C. J. Myers,
"Timed circuit verification using TEL structures",
in IEEE Transactions on CAD, 20(1): 129-146, January, 2001.
- A. E. Sjogren and C. J. Myers,
"Interfacing synchronous and asynchronous modules within a high-speed
pipeline", in IEEE Transactions on VLSI Systems, 8(5): 573-583, October, 2000.
- W. Belluomini and C. J. Myers,
``Timed state space exploration using POSETs,''
in IEEE Transactions on CAD, 19(5): 501-520, May, 2000.
- C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng,
"Automatic synthesis and verification of gate-level timed circuits",
in IEEE Transactions on CAD, 18(6): 769-786, June, 1999.
- P. A. Beerel, C. J. Myers, and T. H.-Y. Meng,
"Covering conditions and algorithms for the synthesis of speed-independent
circuits", in IEEE Transactions on CAD, 17(3): 205-219, March, 1998.
- C. J. Myers and T. H.-Y. Meng,
"Synthesis of timed asynchronous circuits", in
IEEE Transactions on VLSI Systems, 1(2): 106-119, June, 1993
(Invited Paper).
For a complete
list and links to downloadable copies.
Patents
- R. Ginosar, R. Kol, K. Stevens, P. Beerel, K. Yun, C. Myers, and S. Rotem,
Branch instruction handling in a self-timed marking system,
issued August 3, 1999, patent number 5,931,944.
- R. Ginosar, R. Kol, K. Stevens, P. Beerel, K. Yun, C. Myers, and S. Rotem,
Efficient self-timed marking of lengthy variable length instructions,
issued August 24, 1999, patent number 5,941,982.
- R. Ginosar, R. Kol, K. Stevens, P. Beerel, K. Yun, C. Myers, and S. Rotem,
Apparatus and method for self-timed
marking of variable length instructions having length-affecting prefix
bytes, issued September 7, 1999, patent number 5,948,096.
- R. Ginosar, R. Kol, K. Stevens, P. Beerel, K. Yun, C. Myers, and S. Rotem,
Apparatus and method for parallel
processing and self-timed serial marking of variable length instructions,
issued November 2, 1999, patent number 5,978,899.
Awards
- Best Paper Award ASYNC 2007
- Best Paper Award FinalistASYNC 1999
- Best Paper Award ASYNC 1999
- Teaching commendation for CS/EE 5740 in Fall 1998
- National Science Foundation CAREER Award (1996)
- National Science Foundation Graduate Fellowship (1991)
- Rodman W. Paul History Prize, California Institute of Technology (1991)
- Tau Beta Pi National Honor Society (1991)
- Carnation Merit Award, California Institute of Technology (1990)
- First Prize VLSI Design Contest, California Institute of Technology (1990)
Current Course Web Site
For a complete
list of previous course web sites.
Other Professional Activities
Last updated August 2009