Seeking to create innovative software for solving engineering and scientific problems. Involvement with leading edge circuit design as a design engineer is also preferable. Work well in team environments.
My research interests include digital design, arithmetic circuits, low power methodologies, and asynchronous circuits.
For my masters topic, I will be evaluating stoppable-clocks.
I plan to evaluate them for practicality, pros and cons, reliability, and ease of design.
I am using a locally-clocked, iterative multiplier as a driving
example for this evaluation.
Descriptions of the multiplier and initial stoppable-clock design can
be found in my ARVLSI'01 conference paper. I have
completed layout for the multiplier/stoppable-clocks and submitted the
design for fabrication. Fabrication was made possible by
the generosity of MOSIS
. The layout plot for my chip (3x3 mm) can be seen
here. The chip contains a
20-bit multiplier, 3 stoppable-clocks, and testing
circuitry. The multiplier core size (including one clock)
is 0.468 square mm and contains 8190 transistors. The
entire chip contains 26874 transistors. There are two extra stoppable-clocks in the bottom right corner of the chip for testing purposes.
I work in the Timed Circuit Research Group with Chris Myers as my adviser. For more information on our group and research see our website.
Please see vita.
