EDUCATION:
M.S., Electrical Engineering, Shanghai Jiao Tong University, Mar. 1997
B.S., Electrical Engineering, Wuhan
University, July 1994
Research:
I entered this lab on Sep. 1999 and began working as a research assistant since that time. During the fall semester, 1999, I participated in the design of an asynchronous circuit that is used for hearing aid. In this project, my work was mainly focused on the simulation. At the beginning of 2000, I designed an Asynchronous A/D converter that arises me great interest in asynchronous circuit design. Then, I participated in the research project Mixed Analog/Asynchronous VLSI Implementations of Communications Systems. In this project, my work is mainly concentrated on the design methodology for analog VLSI implementations of error control coding systems. My work includes automatic synthesis and automatic simulation of the analog error control coding systems as well as circuit design issues that are aimed to optimize the circuit in a combined consideration of performance, speed, area and power.
Tools:
An automatic simulation tool analog_sim and an automatic synthesis tool analog_syn have been built. The automatic simulation tool can do both high-level ideal behavioral simulation and cell level based simulation. Also, for simulation, several support VHDL files support VHDL files need to be used together with the generated VHDL files to do simulation. For cell level simulation, a VHDL file cell_entity.vhd containing the interface description of the cells need to be provided when using the tool analog_sim. Also, an additional support VHDL file containing the behavioral description of the cells need to be used when doing simulation. If different behavior description of the cells is provided, different result can be obtained. Currently, there are two different descritpion of the cell library, cell_behavior.vhd which uses the one pole system model while the other is cell_qudratic.vhd which uses the qudratic behavior model when the circuit is working at strong or moderate region. For synthesis, one support VHDL file analog_cell.vhd and one support Verilog file analog_cell.v describing the cell interface are provided. The VHDL file should be used when using the tool analog_syn. Then, the generated VHDL files should be used by Synopsys to generate a verilog file describing the decoder. This Verilog file is used together with the interface description Verilog file, the lef file analog_cell.lef for the cell library and the cell library conatining schematic, symbol, layout of the cells to generate the schematic and layout of the decoder. If you like to build a cell library yourself. Then you need to provide the VHDL and Verilog interface files. Also, you need to generate the lef file. If you uses NCSU_AMI06 technology in creating the cell library, then the layout map table file stream.txt and a initial lef file ncsu_ami06_abgen.lef which are needed to generate the lef file are provided. The factor graph description of the extended Hamming (8,4) decoder and "full version" (16,11)^2 product decoder are provided as examples. The generated circuit for the extended Hamming (8,4) decoder and "full version" (16,11)^2 product decoder are also provided.
Publications: