Low Power Synchronous to Asynchronous to Synchronous Interlocked Pipelined CMOS (IPCMOS) Operating at 3.3 - 4.5GHZ

Stan Schuster and Pete Cook

IBM Corporation

To appear at 2001 Advanced Research in VLSI Conference, Salt Lake City, UT, 14-16 March 2001

Abstract

Low power asynchronous circuit techniques suitable for multi - GHz operation use interlocked local clocks. These circuits drive a path through a typical 64b multiplier stage at 3.3 - 4.5 GHz in 0.18um technology. A method for interfacing these asynchronous circuits between synchronous boundaries will also be described

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