Asynchronous Array Multiplier with an Asymmetric Parallel Array Structure

Chan-Ho Park, Byung-Soo Choi, Dong-Ik Lee, and Ho-Yong Choi

To appear at 19th Conference on Advanced Research in VLSI (ARVLSI01), Salt Lake City, UT, 14-16 March 2001


Abstract

In this paper an asynchronous array multiplier with a new parallel structure is introduced. This parallel array structure is designed to make the computation time faster with a lower power consumption. Asymmetric array structure is used to minimize the average calculation time in an asynchronous multiplier. Simulation shows that this structure reduces the time needed for computation by 55% as compared to conventional booth encoding array structures and that the multiplier with the proposed array structure shows a reduction of 25% in the computational time with a relatively lower power consumption.


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