With minor modification to the normal circuit models, SPICE can calculate
transistor widths for near-minimum delay. The same logic gate symbols and the
same connections between them enter into two separate simulations, a "width"
simulation and an "analog" simulation. For the width simulation each logic gate
symbol contains a simple DC circuit modeling the amount of input charge that the
logic gate must absorb to drive its particular load. The width simulation
computes a DC voltage for each logic gate proportional to how wide its
transistors should be for near-minimum overall delay.
After the width simulation has assigned a width to every transistor -- a
relatively brief computation -- the analog simulation proceeds in the usual way.
Because the width simulation makes the width of each transistor proportional to
its total load, the analog simulation finds that all logic gates have nearly the
same delay and that all output transitions have nearly the same shape. The
analog simulation also reveals a remarkably high operating speed and
near-minimum delay throughout the circuit modeled.
Of course the analog results simulated by SPICE now look wonderful, because the
linear DC width model sets transistor widths to be exactly what a linear analog
simulator like SPICE needs for near-optimum results. What does this say about
real chips? Real chips designed using this technique run real fast.
