This paper presents a new approach to two-level hazard-free sum-of-products
logic minimization. No currently available minimizers for literal-exact
two-level hazard-free logic minimization can handle large circuits without
synthesis times ranging up over thousands of seconds.
The logic minimization approach presented in this paper is based on
state graph exploration in conjunction with single-cube cover algorithms.
Our algorithm achieves fast logic minimization by leveraging compacted state
graphs and cover tables and an efficient algorithm for single-output
minimization. Our exact two-level hazard-free logic minimizer
finds minimal number of literal solutions and is significantly faster than
existing literal-exact methods for burst-mode benchmarks, and more than two
orders of magnitude faster for the largest extended burst-mode benchmarks
to date. This includes a benchmark that has never been possible to
solve exactly in number of literals before.
