Abstract- A noise cancellation circuit was designed to improve the
performance of a single-ended source-synchronous I/O interface.
Common-mode variations between the high-frequency data bits and
the DC reference they are compared against were nulled using
negative feedback. The clock and its complement where filtered at
the receiving chip to establish an average value. That value was
fed into a differential amplifier in a feedback loop which corrected
the biasing of the I/O receivers such that the clocks were received
with near 50% duty-cycle (thereby nulling out DC offsets that
typically limit I/O bandwidth). The biasing is shared with all I/O
receivers. A prototype was designed in the HP-14B CMOS process and
demonstrated with a current-mode I/O receiver that was developed
simultaneously. The circuit was designed to operate with a 2.5V power
supply. Measured results indicated that the noise cancellation
circuit improved the receiver bandwidth by 12% (1020-Mb/s vs.
910-Mb/s) and the power-supply gradient rejection capabilities
of the interface improved by almost four times (DVDD=750-mV vs.
DVDD=200-mV).
