Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the restoring character of the logic family, including its high noise margins. Speedups of 2Xƒnto 3X over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to random logic benchmarks. Such speedups are obtained using identical netlists without remapping. When applied to pseudo-nMOS and dynamic families in combination with remapping to wide-input NORs, OPL yields even greater speed-ups over static CMOS. In this paper we present a novel 64-bit adder design implemented in OPL, using a combination of 8-bit Carry Look Ahead and Carry Select. By using an 8-bit CLA instead of the usual 4-bit, we enable the use of fast wide-input OPL NORs. Using a process-independent metric for comparison, this adder is twice as fast as previously published 64-bit adders.
