This work presents new techniques to evaluate flip-flop and latch performance and shows that no existing single flip-flop or latch design gives good
energy and delay performance across the wide range of operating regimes present in complex systems. We propose the use of a selection of flip-flop and
latch designs, each tuned for different activation patterns and speed requirements. We illustrate the use of our technique on a pipelined MIPS processor
datapath running SPECint benchmarks, where we reduce total flip-flop and latch energy by over 60% without increasing cycle time.
