The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisfied through the use of a shared bus. A common alternative, using unidirectional, point-to-point connections and multiplexers, results in much greater area requirements and still suffers from some of the same problems.
This paper introduces a delay-insensitive, asynchronous approach to interconnect over long paths using 1-of-4 encoded channels switched through multiplexers. A re-implementation of the MARBLE SoC bus, as used in the AMULET3H, chip using this technique shows that it can provide a higher throughput than the simpler tristate bus while using a narrower datapath. This benefit is in addition to the significant time savings that can be made at the design validation stage by using a delay insenstive approach
