Representing events as pulses of fixed and short duration combines the
understandability of a return-to-zero representation and the simplicity of a
non-return-to-zero representation. Like the return-to-zero or "four-phase"
representation, a pulse has HI and LO intervals that simplify understanding.
Like the non-return-to-zero or "two-phase" representation, a pulse avoids the
need to compute return transitions, because each return happens after a fixed
time. Because each pulse is of fixed and short duration, pulse circuits must
use transistors with carefully chosen widths.
This paper describes a family of asynchronous pipeline circuits based on pulses.
A single wire that we call a "state conductor" represents the FULL or EMPTY
state of each stage; changes in state carry both request and acknowledge
messages. The family includes circuits for simple FIFO buffers, for branching
and joining pipelines, for round-robin scatter and gather, for data-dependent
scatter and gather, and for join on demand through arbitration. The family is
designed so that each stage operates at the speed of a three-inverter ring
oscillator. Test chips in 0.35 micron technology exhibit throughput in excess
of 1.5 giga data items per second (GDI/s).
