Synchronous implementation of handshake circuits may seem a weird idea at first
glance, since operation dictated by a clock typically conflicts with the low-power
and low-EMI targets set for handshake designs.
However, clocking may have some interesting advantages over
complete asynchrony. Most notably, synchronous implementations tend to
be smaller and faster, are not sensitive to hazards and are easier to test than
the good-old asynchronous implementations.
We have developed a complete synchronous backend for Tangram, which could be
used as a backend towards FPGAs, or as a fall-back option when an asynchronous
implementation runs into test, performance, area, or management-confidence
problems.
Furthermore, synchronous handshake circuits can be used to study new
clock-gating approaches, and to learn why asynchronous implementations are
generally more power friendly.
