In this paper, we present the design and experimental evaluation of an
8-bit adiabatic multiplier with built-in self-test (BIST) logic and an
internal single-phase sinusoidal power-clock generator. Both the
multiplier and the BIST have been designed in SCAL-D, a true
single-phase adiabatic logic family. In HSPICE simulations with
post-layout extracted parasitics, our design functions correctly at
frequencies exceeding 200 MHz, with total dissipation for the
multiplier and BIST circuitry of 91pJ per multiplication at 100MHz.
The chip has been fabricated in a 0.5um standard CMOS process with an
active area of 0.47mm^2. Correct chip operation has been validated
for operating frequencies up to 130MHz, the limit of our experimental
setup. Measured dissipation correlates well with HSPICE simulations
for identical biasing conditions.
