Differential signaling uses double the number of interconnects when compared to single ended signaling. The signal to interconnect usage of a differential signal is (n/2) balanced signals per n interconnects. A method is described which can increase the interconnect usage to (n-1) balanced signals per n wires. The additional bandwidth is achieved by inserting signal information into the common mode signal between two or more interconnects. Simulations in 0.25mm CMOS technology have indicated that bit rates of 1 Gb/s are achievable using the common mode signaling technique. These additional balanced signals can be sent in the same or opposing directions to the original information. Several schemes are described including voltage and current signaling and a bussed structure is proposed. A simple receiver structure is used to extract the common mode signal.
