This paper describes the design of a standard-cell self-timed
multiplier for use in power and area critical synchronous systems.
The area of this multiplier is bounded by N rather than N^2 as
seen in more traditional combinational parallel array designs, where
N is the word size. Power has a polynomial growth with word size, but
has a coefficient that is much smaller than that seen in a
combinational array design. Although the multiplier is self-timed, it
can be embedded in synchronous systems as a combinational element.
This paper presents latency, area, and power estimates for the
multiplier implemented at various word sizes, and compares these
numbers with a traditional combinational array multiplier. The
self-timed multiplier uses 1/3 the power and 1/7
the area of the combinational design for a 24-bit word size.
