This paper presents an evaluation of a range of cache features when applied to an asynchronous, dual-ported cache connected to the AMULET3 asynchronous microprocessor core. It is shown that using a copy-back cache with a victim cache gives just under 10% performance improvement for an 8-kilobyte cache when compared to a simpler write-through architecture. The design presented addresses the issue of providing the AMULET3 core with a unified, dual-ported view of its memory subsystem using multiple interleaved blocks each with separate line-buffers.
