Frontiers in Analog Circuit (FAC) Synthesis and Verification

Co-located with the Computer Aided Verification (CAV) Conference

July 14-15, 2011

Cliff Lodge, Snowbird, Utah

TECHNICAL SPONSORS

IEEE CAS IEEE MTT

WITH GENEROUS SUPPORT FROM

CEDA

and

Intel Corporation


While the development of digital circuits is currently supported by a plethora of EDA tools, the development of analog and mixed-signal (AMS) circuits has lagged behind, remaining essentially an ad-hoc and artistic activity, not facilitating re-use and not easily integrated in a system-level development process. Some of the reasons for this situation are inherent in the technical differences between digital and analog computation while others are due to sociological reasons in the respective communities such as the fact that the cultural distance between the EDA software developers and analog designers is much larger than their distance to digital designers.

With the advent of embedded systems-on-chip, this state of affairs puts the development of analog sub-systems (necessary for all interactions with the physical world) in the critical path of new product development and the semi-conductor industry now realizes that it needs more advanced CAD tools for simulation, verification, test, design-space exploration, model reduction, synthesis and integration with digital sub-systems. The goal of this workshop is to bring together analog designers, EDA tool providers and researchers from the relevant disciplines (verification, simulation, control) to advance the state-of-the-art of AMS synthesis and verification.

Invited Speakers

Workshop Program

Abstracts and Slides

Registration and Accomodations

Registration and accomodation information is available on the CAV 2011 website. If you are not attending CAV, please be sure to register for a two day workshop (2DW).

Call for Abstracts

Abstract Submission: abstracts should be at least 500 words but not more than 1000 words in length; they may contain up to two figures; they should be in PDF form, up to 2 pages in length, with 1-inch margins and at least 10-point font size; they should indicate whether the submission is for a poster presentation, an oral presentation, or both; they should list the full names, affiliations and contact information of all authors. Abstracts will be reviewed by the Program Committee. Those that are selected for oral and poster presentations will distributed to workshop participants and posted on the workshop website. Abstracts should be submitted by April 4th to fac2011@vlsigroup.ece.utah.edu (abstracts submitted after April 4th will still be considered, until the presentation schedule is finalized, but may not receive full consideration).

Topics of Interest

Organizing Committee

Program Committee

Workshop History

This workshop is partly a successor of the FAC (formal verification of analog circuits) workshop held in 2005, 2008, and 2009. Information about past workshops can be found at:

Steering Committee