Frontiers in Analog Circuit (FAC) Synthesis and Verification
July 14-15, 2011
Cliff Lodge, Snowbird, Utah
TECHNICAL SPONSORS
WITH GENEROUS SUPPORT FROM
and
Intel Corporation
While the development of digital circuits is currently supported by a
plethora of EDA tools, the development of analog and mixed-signal
(AMS) circuits has lagged behind, remaining essentially an ad-hoc and
artistic activity, not facilitating re-use and not easily integrated
in a system-level development process. Some of the reasons for this
situation are inherent in the technical differences between digital
and analog computation while others are due to sociological reasons in
the respective communities such as the fact that the cultural distance
between the EDA software developers and analog designers is much
larger than their distance to digital designers.
With the advent of embedded systems-on-chip, this state of affairs
puts the development of analog sub-systems (necessary for all
interactions with the physical world) in the critical path of new
product development and the semi-conductor industry now realizes that
it needs more advanced CAD tools for simulation, verification, test,
design-space exploration, model reduction, synthesis and integration
with digital sub-systems. The goal of this workshop is to bring
together analog designers, EDA tool providers and researchers from the
relevant disciplines (verification, simulation, control) to advance
the state-of-the-art of AMS synthesis and verification.
Invited Speakers
Workshop Program
Abstracts and Slides
Registration and Accomodations
Registration and accomodation information is available on the CAV 2011 website. If you are not attending CAV, please be sure to register for a two day workshop (2DW).
Call for Abstracts
Abstract Submission: abstracts should be at least 500 words but not more than 1000 words in length; they may contain up to two figures; they should be in PDF form, up to 2 pages in length, with 1-inch margins and at least 10-point font size; they should indicate whether the submission is for a poster presentation, an oral presentation, or both; they should list the full names, affiliations and contact information of all authors. Abstracts will be reviewed by the Program Committee. Those that are selected for oral and poster presentations will distributed to workshop participants and posted on the workshop website. Abstracts should be submitted by April 4th to fac2011@vlsigroup.ece.utah.edu (abstracts submitted after April 4th will still be considered, until the presentation schedule is finalized, but may not receive full consideration).
- Submission deadline: April 4, 2011
- Acceptance notification: May 4, 2011
- Final version due: May 25, 2011
Topics of Interest
- Modeling approaches for analog circuits at different levels of
abstraction
- Verification of continuous models using hybrid system techniques
- Model checking and theorem proving methods
- Using assertions to detect errors during simulation (and for post-
fabrication testing)
- Fast simulation of AMS circuits
- Parameter space exploration
- Component-based methodology for AMS circuits
- Analysis of timing, power, and heat
- Methods at intersection of verification, test, and post-Si diagnosis
- Correct-by-construction approaches to AMS design, including synthesis
- Analog reuse
Organizing Committee
- Program Chair:
Chris J. Myers, University of Utah
- Program Chair: Kevin Jones, City University London
- Industrial Liaison: Jeff Parkhurst, Intel
Program Committee
- Jacob Abraham, University of Texas, Austin
- Fadi Gebara, IBM
- Mark Greenstreet, University of British Columbia
- Christoph Grimm, TU Wien, Austria
- Lars Hedrich, Johann Wolfgang Goethe-Universität
- Mark Horowitz, Stanford University
- Qi Jing, Mentor
- Yaron Kashai, Cadence
- Chandramouli Kashyap, Intel Corporation
- Jaeha Kim, Seoul National University
- Peng Li, Texas A&M
- Scott Little, Freescale
- Oded Maler, Verimag
- Michel Nakhla, Carleton University
- Dejan Nickovic, Institute of Science and Technology (IST) Austria
- Rob Rutenbar, University of Illinois at Urbana-Champaign
- Sofiene Tahar, Concordia University
Workshop History
This workshop is partly a successor of the FAC (formal
verification of analog circuits) workshop held in 2005, 2008, and 2009.
Information about past workshops can be found at:
Steering Committee