Triscuit's Control State Machine

The purpose of the control state machine is to generate the signals necessary to execute instructions through the data path. The overall block diagram of the control state machine is shown in figure 2.

  
Figure 2: Triscuit's Control State Machine

This figure shows the inputs to the state machine that come from the data path, and the outputs of the machine that control the data path. The inputs on the top of the block are RESET, used to set the machine into an initial state (note that this is the same signal that clears the values of the IR and PC to 0 in the datapath), and CLOCK which is the system clock.

The inputs on the left of Figure 2 come from the data path. The GO signal is actually a switch that will determine whether the processor should execute instructions or not. The very first state of the control state machine should check this value and state in the initial state until GO is asserted.

The next five inputs are generated from the value in the instruction register. Each of these signals should be asserted if the processor is currently executing that type of instruction. These signals are simply logic that looks at the value in the instruction register and decided which type of instruction is held there according to the four bit opcode. The instruction encoding is particularly simple for Triscuit to minimize this decoding. The encoding is shown in Figure 3.

  
Figure 3: Opcode Values for Triscuit Instructions

Finally, the last input to the state machine is a value that comes from the data path to tell if the current accumulator value is 0. This is used to decide whether to take a branch or not.

The outputs from the control state machine are connected to circuits in the data path. They are as follows:

Add-Sub

-- A signal that is 1 if the processor is doing a subtraction, and 0 otherwise.

Ld-Acc

-- A signal that causes the accumulator register to latch a new value.

Clr-Acc

-- A signal that causes the accumulator to clear itself to 0.

Ld-Inst

-- A signal that causes the instruction register to latch a new value.

Ld-PC

-- A signal to the PC that will cause it to load a new four bit value on the next system clock.

Incr-PC

-- A signal that will cause the PC to increment by one on the next system clock signal.

Addr-Sel

-- A signal that will be low whenever the PC should be used as the memory address, and high when the value in the instruction register should be used as the memory address.

Rbar-W

-- A signal sent to the ``memory'' that is 0 if you are doing a read and 1 if you are doing a write.

The operation of the state machine should cause these control signals to be asserted in the proper order to execute Triscuit's instruction set.

1. Check to see that the GO signal is asserted.
2. Use the PC to fetch the next instruction
3. Store the current instruction in the instruction register
4. Increment the PC value
5. Decode the opcode to decide what to do next
   • ADD or SUB
     1. Get another value from memory
     2. do requested ALU op
     3. latch result in ACC
   • CLR
     1. clear the ACC
   • STORE
     1. get next value from memory as address to store to. Store this in the instruction latch
     2. enable instruction latch to memory as the address
     3. do memory write cycle using ACC as data
   • BNZ
     1. Get next value from memory as address to branch to, put it in the instruction register
     2. Load that value into the PC
6. Increment the PC again if necessary
7. Repeat

• Triscuit's Memory
• Triscuit's Clock